Related papers: FPGA Implementation of RDMA-Based Data Acquisition…
The IEEE 802.15.4 is a wireless standard introduced for low power, low cost wireless communication with moderate data rates. In the next few years, it is expected that Low Rate Wireless Personal Area Networks (LR-WPAN) will be used in a…
Security is the most important part in data communication system, where more randomization in secret keys increases the security as well as complexity of the cryptography algorithms. As a result in recent dates these algorithms are…
With the rapidly-developing high-speed wireless communications, the 60 GHz millimeter-wave frequency range and radio-over-fiber systems have been investigated as a promising solution to deliver mm-wave signals. Neural networks have been…
Next generation Wi-Fi networks are expected to support real-time applications that impose strict requirements on the packet transmission delay and packet loss ratio. Such applications form an essential target for the future Wi-Fi standard,…
RDMA is vital for efficient distributed training across datacenters, but millisecond-scale latencies complicate the design of its reliability layer. We show that depending on long-haul link characteristics, such as drop rate, distance and…
Emerging wireless applications such as 5G cellular, large intelligent surfaces (LIS), and holographic massive MIMO require antenna array processing at mm-wave frequencies with large numbers of independent digital transceivers. This paper…
Achieving low remote memory access latency remains the primary challenge in realizing memory disaggregation over Ethernet within the datacenters. We present EDM that attempts to overcome this challenge using two key ideas. First, while…
With the rapid development of network protocol, TCP/IP has been widely applied in various OS systems because of its advantages of high-speed network transmission and standardization. Furthermore, TCP/IP has the functions of retransmission…
Edge AI deployment faces critical challenges balancing computational performance, energy efficiency, and resource constraints. This paper presents FPGA-accelerated RISC-V instruction set architecture (ISA) extensions for efficient neural…
Digital off-detector electronics in trigger and data acquisition systems of High-Energy Physics experiments is often implemented by means of SRAM-based FPGAs, which make it possible to achieve reconfigurable, real-time processing and…
Remote Direct Memory Access (RDMA) is a technology that allows direct memory access from the memory of one computer into that of another without involving either one's operating system. This enables high-throughput, low-latency networking,…
The need for a high-performance transceiver with high Signal to Noise Ratio (SNR) has driven the communication system to utilize the latest technique identified as oversampling systems. It was the most economical modulator and decimation in…
User Datagram Protocol (UDP) is a commonly used protocol for data transmission in small embedded systems. UDP as such is unreliable and packet losses can occur. The achievable data rates can suffer if optimal packet sizes are not used. The…
We introduce an open-source architecture for next-generation Radio-Access Network baseband processing: 1024 latency-tolerant 32-bit RISC-V cores share 4 MiB of L1 memory via an ultra-low latency interconnect (7-11 cycles), a modular Direct…
The ongoing revolution in application domains targeting autonomous navigation, first and foremost automotive "zonalization", has increased the importance of certain off-chip communication interfaces, particularly Ethernet. The latter will…
We present an overview of the 'ICE' hardware and software framework that implements large arrays of interconnected FPGA-based data acquisition, signal processing and networking nodes economically. The system was conceived for application to…
We develop a custom Bit Error Rate test bench based on Altera's Stratix II GX transceiver signal integrity development kit, demonstrate it on point-to-point serial optical link with data rate up to 5 Gbps, and compare it with commercial…
An ultra-high-speed waveform digitizer prototype based on gigabit Ethernet has been developed. The prototype is designed to read out signals of detectors to realize the accurate measurement of various physical quantities for plasma…
In this paper we have addressed the implementation of the accumulation and projection of high-resolution event data stream (HD -1280 x 720 pixels) onto the image plane in FPGA devices. The results confirm the feasibility of this approach,…
FPGA overlays are commonly implemented as coarse-grained reconfigurable architectures with a goal to improve designers' productivity through balancing flexibility and ease of configuration of the underlying fabric. To truly facilitate full…