Related papers: A Phase Lookahead DTC for Fast Settling Switched L…

In this paper, we demonstrate a simple scheme of 6.835 GHz microwave frequency synthesizer based on the sub-sampling phase lock loop (PLL) technique. The application of the sub-sampling PLL is the key to simplify the architecture of the…

A 3.8ps root mean square (RMS) time synchronization implemented in a 20nm fabrication process ultrascale kintex Field Programmable Gate Array (FPGA) is presented. The multichannel high-speed serial transceivers (e.g. GTH) play a key role in…

A novel quadrature Doppler Backscattering (DBS) system has been developed and optimized for the E-band (60-90GHz) frequency range using either O-mode or X-mode polarization in DIII-D plasmas. In general, DBS measures the amplitude of…

Dynamic time division duplexing (TDD) is one of the major novelties of the 5G new radio standard. It notably improves the network resource utilization with sporadic directional packet arrivals. Although, the feasibility of the…

Discrete Fractional Fourier Transforms (DFrFT) are universal mathematical tools in signal processing, communications and microwave sensing. Despite the excessive applications of DFrFT, implementation of corresponding fractional orders in…

This study introduces a Block Phase Tracking Reference Signal (PTRS) allocation approach for Discrete Fourier Transform-spread-Orthogonal Frequency Division Multiplexing (DFT-s-OFDM) systems to enhance phase noise tracking and compensation.…

The delay-Doppler (DD) domain modulation has been regarded as one of the most competitive candidates to support wireless communications for emerging high-mobility applications in the sixth-generation mobile networks. Unfortunately, most of…

Today, wide-open, high-resolution Doppler frequency shift (DFS) estimation is essential for radar, microwave/millimeter-wave, and communication systems. Using photonics technology, an effective approach is proposed and experimentally…

- This paper describes a pipeline analog-to-digital converter is implemented for high speed camera. In the pipeline ADC design, prime factor is designing operational amplifier with high gain so ADC have been high speed. The other advantage…

The upgrade of the ATLAS muon spectrometer for high-luminosity LHC requires new trigger and readout electronics for the various elements of the detector. We present the design of a time-to-digital converter (TDC) ASIC prototype for the…

In Orthogonal Time Frequency Space (OTFS) modulation, information symbols are embedded in the delay-Doppler (DD) domain instead of the time-frequency (TF) domain. n order to ensure compatibility with existing OFDM systems (e.g. 4G LTE),…

In this work, we propose a deep learning (DL)-based approach that integrates a state-of-the-art algorithm with a time-frequency (TF) learning framework to minimize overall latency. Meeting the stringent latency requirements of 6G orthogonal…

The quantum charge-coupled device (QCCD) is one of the notable architectures to achieve large-scale trapped-ion quantum computers. To realize QCCD architecture, ions must be transported quickly while minimizing motional excitation.…

This paper presents a novel strategy for the synchronization of grid-following Voltage Source Converters (VSCs) in power systems with low rotational inertia. The proposed synchronization unit is based on emulating the physical properties of…

We present the second prototype of a time-to-digital (TDC) ASIC for the upgrade of the ATLAS Monitored Drift Tube (MDT) detector for High-Luminosity LHC operations. Compared to the first prototype, triple modular redundancy has been…

High-performance two-qubit gates have been reported with superconducting qubits coupled via a single-transmon coupler (STC). Most of them are implemented for qubits with a small detuning since reducing residual $ZZ$ coupling for highly…

Grid-interactive power converters are normally synchronized to the grid using phase-locked loops (PLLs). The performance of the PLLs is affected by the non-ideal conditions in the sensed grid voltage such as harmonics, frequency deviations…

This paper presents a low hardware consumption, resolution-configurable, automatically calibrating Gray code oscillator time-to-digital converter (TDC) in Xilinx 16nm UltraScale+, 20nm UltraScale and 28nm Virtex-7 field-programmable gate…

We propose dynamic resistive threshold-logic (DRTL) design based on non-volatile resistive memory. A threshold logic gate (TLG) performs summation of multiple inputs multiplied by a fixed set of weights and compares the sum with a…

The GANDALF 6U-VME64x/VXS module has been designed to cope with a variety of readout tasks in high energy and nuclear physics experiments, in particular the COMPASS experiment at CERN. The exchangeable mezzanine cards allow for an…