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The fast-rising demand for wireless bandwidth requires rapid evolution of high-performance baseband processing infrastructure. Programmable many-core processors for software-defined radio (SDR) have emerged as high-performance baseband…
Rivest-Shamir-Adleman (RSA) cryptosystem uses modular multiplication for encryption and decryption. So, performance of RSA can be drastically improved by optimizing modular multiplication. This paper proposes a new parallel, high-radix…
BCH (Bose-Chaudhuri-Hocquenghen) error correcting codes ([1]-[2]) are now widely used in communication systems and digital technology. Direct LFSR(linear feedback shifted register)-based encoding of a long BCH code suffers from serial-in…
Parsing is essential for a wide range of use cases, such as stream processing, bulk loading, and in-situ querying of raw data. Yet, the compute-intense step often constitutes a major bottleneck in the data ingestion pipeline, since parsing…
The utilization of finite field multipliers is pervasive in contemporary digital systems, with hardware implementation for bit parallel operation often necessitating millions of logic gates. However, various digital design issues, whether…
Polar codes are a new class of block codes with an explicit construction that provably achieve the capacity of various communications channels, even with the low-complexity successive-cancellation (SC) decoding algorithm. Yet, the more…
Large language models (LLMs) often face a bottleneck in inference speed due to their reliance on auto-regressive decoding. Recently, parallel decoding has shown significant promise in enhancing inference efficiency. However, we have…
A novel recursive list decoding (RLD) algorithm for Reed-Muller (RM) codes based on successive permutations (SP) of the codeword is presented. A low-complexity SP scheme applied to a subset of the symmetry group of RM codes is first…
Reconfigurable intelligent surfaces (RISs) have become a promising candidate for the development of future mobile systems. In the context of massive machine-type communications (mMTC), a RIS can be used to support the transmission from a…
We present two prototypes of a gigabit transceiver ASIC, GBCR1 and GBCR2, both designed in a 65-nm CMOS technology for the ATLAS Inner Tracker Pixel Detector readout upgrade. The first prototype, GBCR1, has four upstream receiver channels…
Digital off-detector electronics in trigger and data acquisition systems of High-Energy Physics experiments is often implemented by means of SRAM-based FPGAs, which make it possible to achieve reconfigurable, real-time processing and…
We present a novel error correcting code and decoding algorithm which have construction similar to expander codes. The code is based on a bipartite graph derived from the subsumption relations of finite projective geometry, and Reed-Solomon…
Polar codes have become one of the most favorable capacity achieving error correction codes (ECC) along with their simple encoding method. However, among the very few prior successive cancellation (SC) polar decoder designs, the required…
This paper presents 6T SRAM cell-based bit-parallel in-memory computing (IMC) architecture to support various computations with reconfigurable bit-precision. In the proposed technique, bit-line computation is performed with a short WL…
A new variant of bit interleaved coded modulation (BICM) is proposed. In the new scheme, called Parallel BICM, L identical binary codes are used in parallel using a mapper, a newly proposed finite-length interleaver and a binary dither…
Even though polar codes were adopted in the latest 5G cellular standard, they still have the fundamental problem of high decoding latency. Aiming at solving this problem, a fast simplified successive cancellation (Fast-SSC) decoder based on…
5G New Radio (NR) has stringent demands on both performance and complexity for the design of low-density parity-check (LDPC) decoding algorithms and corresponding VLSI implementations. Furthermore, decoders must fully support the wide range…
Traditional Real-Time Operating Systems (RTOS) often suffer from limited parallel performance, whereas thread monitoring in Linux-based systems remains challenging. To overcome these limitations, this paper presents a satellite flight…
Reed-Muller (RM) and polar codes are a class of capacity-achieving channel coding schemes with the same factor graph representation. Low-complexity decoding algorithms fall short in providing a good error-correction performance for RM and…
With the emergence of low-cost robotic systems, such as unmanned aerial vehicle, the importance of embedded high-performance image processing has increased. For a long time, FPGAs were the only processing hardware that were capable of…