Related papers: A programmable clock generator for automatic Quali…

This paper addresses the mathematical modeling and compensation of stochastic discrete-time clock jitter in analog-to-digital converters (ADCs). We model the stochastic clock jitter as a first-order autoregressive (AR(1)) process, and we…

A prototype optical-link board has been developed for the ATLAS Liquid Argon Calorimeter Phase-2 upgrade. The board consists of 24 lpGBT chips and 8 VTRx+ modules and demonstrates the full optical link design of the future front-end board.…

A frequency stabilized laser referenced to an unperturbed atomic two level system acts as the most accurate clock with femtosecond clock ticks. For any meaningful use, a Femtosecond Laser Frequency Comb (FLFC) is used to transfer the atomic…

We have commissioned the digital Low Level RF (LLRF) system for storage ring RF at Advanced Light Source at Lawrence Berkeley National Lab (LBNL). The system is composed of 42 synchronous sampling channels for feedback control, diagnostics,…

In this work, a long-cavity semiconductor laser subject to optical feedback is exploited to generate repetitive temporal patterns with enhanced intra-pattern sample diversity. Stable limit cycle dynamics characterized by multiple frequency…

The challenging demands of the ATLAS High Luminosity (HL-LHC) Upgrade aim for a complete swap of new generation sensors that should cope with the ultimate radiation hardness. FBK has been one of the prime foundries to develop and fabricate…

This paper presents the design and characterisation of a front-end prototype ASIC for the ATLAS High Granularity Timing Detector, which is planned for the High-Luminosity phase of the LHC. This prototype, called ALTIROC1, consists of a…

The ongoing work to upgrade ALS to ALS-U demands strict RF requirements such as low jitter and low spurs frequency reference to meet its accelerator and science goals. A low phase noise dual frequency Master Oscillator (MO), where the two…

We present the design and test results of two optical data transmission ASICs for the High-Luminosity LHC (HL-LHC) experiments. These ASICs include a two-channel serializer (LOCs2) and a single-channel Vertical Cavity Surface Emitting Laser…

Three generations of full-custom analog integrated circuits designed for low-power, high-speed sampling of Radio-Frequency (RF) transients in excess of the Nyquist minimum have been developed. These 0.25$\mu m$ CMOS devices are denoted the…

This article theoretically proposes a new dual interferometer technique to accurately calibrate two laser frequencies simultaneously using four-wave mixing in an alkali metal vapor cell. The two frequency-calibrated lasers are mixed to…

The LHC will undergo a major upgrade starting in 2025 towards the High Luminosity LHC (HL-LHC) to increase the instantaneous luminosity by a factor of 5 to 7 compared to the nominal value. The Phase-II Upgrade (2025-2027) will require the…

In order to achieve the driver function for several types of scientific CCD detector from E2V Co Ltd, and decreasing the size of electronics of CCD detector system, an Application-specified Integrated Circuit (ASIC) was designed. It…

The ABCStar is a mixed-signal front-end readout ASIC for the strips sensor portion of the ATLAS ITk detector being developed as part of the High-Luminosity LHC upgrade. In pre-production testing, a subtle design flaw was uncovered in the…

In a wide range of quantum technology applications, ranging from atomic clocks to the creation of ultracold or quantum degenerate samples for atom interferometry, optimal laser sources are critical. In particular, two phase-locked laser…

In TDC testing or timing system implementation tasks, it is often desirable to generate signal pulses with fine adjustable time intervals. In delay cell-based schemes, the time adjustment steps are limited by the propagation delays of the…

We present the second prototype of a time-to-digital (TDC) ASIC for the upgrade of the ATLAS Monitored Drift Tube (MDT) detector for High-Luminosity LHC operations. Compared to the first prototype, triple modular redundancy has been…

We demonstrate a hybrid analog+digital electronic lock to stabilize a dynamically tunable rf offset between two lasers. Our method features an 80 MHz capture range, +/- 7 GHz tuning range, frequency agility of 1 MHz/microsecond, and low…

We have designed three ASICs for possible applications in the optical links of a new layer of pixel detector in the ATLAS experiment for the first phase of the LHC luminosity upgrade. The ASICs include a high-speed driver for the VCSEL, a…

The Phase-2 ATLAS upgrade for the High Luminosity Large Hadron Collider (HL-LHC) has motivated progressive redesigns of the ATLAS Tile Calorimeter (TileCal) read-out link and control board (Daughterboard). The Daughterboard (DB)…