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Runahead execution is a technique to mask memory latency caused by irregular memory accesses. By pre-executing the application code during occurrences of long-latency operations and prefetching anticipated cache-missed data into the cache…

Hardware Architecture · Computer Science 2025-04-03 Dean You , Jieyu Jiang , Xiaoxuan Wang , Yushu Du , Zhihang Tan , Wenbo Xu , Hui Wang , Jiapeng Guan , Zhenyuan Wang , Ran Wei , Shuai Zhao , Zhe Jiang

Computing has a huge memory problem. The memory system, consisting of multiple technologies at different levels, is responsible for most of the energy consumption, performance bottlenecks, robustness problems, monetary cost, and hardware…

Hardware Architecture · Computer Science 2025-09-05 Onur Mutlu , Ataberk Olgun , Ismail Emir Yuksel

Advancements in multi-core have created interest among many research groups in finding out ways to harness the true power of processor cores. Recent research suggests that on-board component such as cache memory plays a crucial role in…

Hardware Architecture · Computer Science 2011-11-15 N. Ramasubramanian , Srinivas V. V. , N. Ammasai Gounden

Bulk-bitwise processing-in-memory (PIM), where large bitwise operations are performed in parallel by the memory array itself, is an emerging form of computation with the potential to mitigate the memory wall problem. This paper examines the…

Hardware Architecture · Computer Science 2023-09-29 Ben Perach , Ronny Ronen , Benny Kimelfeld , Shahar Kvatinsky

Stacked intelligent metasurface (SIM) is an emerging technology that uses multiple reconfigurable surface layers to enable flexible wave-based beamforming. In this paper, we focus on an \ac{SIM}-assisted multi-user multiple-input…

Signal Processing · Electrical Eng. & Systems 2025-04-22 Nipuni Ginige , Prathapasinghe Dharmawansa , Arthur Sousa de Sena , Nurul Huda Mahmood , Nandana Rajatheva , Matti Latva-aho

We investigate and characterize the performance of an important class of operations on GPUs and Many Integrated Core (MIC) architectures. Our work is motivated by applications that analyze low-dimensional spatial datasets captured by high…

Distributed, Parallel, and Cluster Computing · Computer Science 2013-11-05 George Teodoro , Tahsin Kurc , Jun Kong , Lee Cooper , Joel Saltz

Managing interference in a network of macrocells underlaid with femtocells presents an important, yet challenging problem. A majority of spatial (frequency/time) reuse based approaches partition the users based on coloring the interference…

Information Theory · Computer Science 2015-04-28 Kartik Ahuja , Yuanzhang Xiao , Mihaela van der Schaar

The substantial memory demands of pre-training and fine-tuning large language models (LLMs) require memory-efficient optimization algorithms. One promising approach is layer-wise optimization, which treats each transformer block as a single…

Machine Learning · Computer Science 2026-01-15 Yuxi Liu , Renjia Deng , Yutong He , Xue Wang , Tao Yao , Kun Yuan

The performance levels of a computing machine running a given workload configuration are crucial for both users and providers of computing resources. Knowing how well a computing machine is running with a given workload configuration is…

Distributed, Parallel, and Cluster Computing · Computer Science 2020-12-16 Lorenzo Luciano , Imre Kiss , Peter William Beardshear , Esther Kadosh , A. Ben Hamza

Test-time compute scaling has emerged as a powerful paradigm for enhancing mathematical reasoning in large language models (LLMs) by allocating additional computational resources during inference. However, current methods employ uniform…

Computation and Language · Computer Science 2025-12-02 Yang Xiao , Chunpu Xu , Ruifeng Yuan , Jiashuo Wang , Wenjie Li , Pengfei Liu

Measuring Mutual Information (MI) between high-dimensional, continuous, random variables from observed samples has wide theoretical and practical applications. Recent work, MINE (Belghazi et al. 2018), focused on estimating tight…

Machine Learning · Computer Science 2019-05-28 Xiao Lin , Indranil Sur , Samuel A. Nastase , Ajay Divakaran , Uri Hasson , Mohamed R. Amer

Data movement between memory and processors is a major bottleneck in modern computing systems. The processing-in-memory (PIM) paradigm aims to alleviate this bottleneck by performing computation inside memory chips. Real PIM hardware (e.g.,…

Hardware Architecture · Computer Science 2023-10-04 Jinfan Chen , Juan Gómez-Luna , Izzat El Hajj , Yuxin Guo , Onur Mutlu

Modern applications increasingly rely on inference serving systems to provide low-latency insights with a diverse set of machine learning models. Existing systems often utilize resource elasticity to scale with demand. However, many…

Distributed, Parallel, and Cluster Computing · Computer Science 2025-05-13 Joel Wolfrath , Daniel Frink , Abhishek Chandra

In many embedded real-time systems, applications often interact with I/O devices via read/write operations, which may incur considerable suspension delays. Unfortunately, prior analysis methods for validating timing correctness in embedded…

Other Computer Science · Computer Science 2014-07-22 Guangmo Tong , Cong Liu

Next-generation supercomputers will feature more hierarchical and heterogeneous memory systems with different memory technologies working side-by-side. A critical question is whether at large scale existing HPC applications and emerging…

Distributed, Parallel, and Cluster Computing · Computer Science 2017-04-27 Ivy Bo Peng , Stefano Markidis , Erwin Laure , Gokcen Kestor , Roberto Gioiosa

Container orchestration technologies are widely employed in cloud computing, facilitating the co-location of online and offline services on the same infrastructure. Online services demand rapid responsiveness and high availability, whereas…

Distributed, Parallel, and Cluster Computing · Computer Science 2024-02-15 Xiang Li , Linfeng Wen , Minxian Xu , Kejiang Ye

Maximal Independent Set (MIS) is one of the fundamental problems in distributed computing. The round (time) complexity of distributed MIS has traditionally focused on the \emph{worst-case time} for all nodes to finish. The best-known…

Distributed, Parallel, and Cluster Computing · Computer Science 2020-06-16 Soumyottam Chatterjee , Robert Gmyr , Gopal Pandurangan

The vast number of interleavings that a concurrent program can have is typically identified as the root cause of the difficulty of automatic analysis of concurrent software. Weak memory is generally believed to make this problem even…

Logic in Computer Science · Computer Science 2013-01-09 Jade Alglave , Daniel Kroening , Michael Tautschnig

In this paper, we propose an empirical method for evaluating the performance of parallel code. Our method is based on a simple idea that is surprisingly effective in helping to identify causes of poor performance, such as high…

Distributed, Parallel, and Cluster Computing · Computer Science 2017-09-15 Umut A. Acar , Arthur Charguéraud , Mike Rainey

Conventional cache models are not suited for real-time parallel processing because tasks may flush each other's data out of the cache in an unpredictable manner. In this way the system is not compositional so the overall performance is…

Hardware Architecture · Computer Science 2011-11-09 A. M. Molnos , M. J. M. Heijligers , S. D. Cotofana , J. T. J. Van Eijndhoven