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Large language models (LLMs) have demonstrated exceptional proficiency in understanding and generating human language, but efficient inference on resource-constrained embedded devices remains challenging due to large model sizes and…

Hardware Architecture · Computer Science 2025-07-15 Weihong Xu , Haein Choi , Po-kai Hsu , Shimeng Yu , Tajana Rosing

The rise of intelligent autonomous systems, especially in robotics and autonomous agents, has created a critical need for robust communication middleware that can ensure real-time processing of extensive sensor data. Current robotics…

Robotics · Computer Science 2024-12-03 Jacky Kwok , Shulu Li , Marten Lohstroh , Edward A. Lee

Today, there is a trend to incorporate more intelligence (e.g., vision capabilities) into a wide range of devices, which makes high performance a necessity for computing systems. Furthermore, for embedded systems, low power consumption…

Other Computer Science · Computer Science 2014-08-25 Zhilei Chai , Zhibin Wang , Wenmin Yang , Shuai Ding , Yuanpu Zhang

Large-scale distributed computing infrastructures such as the Worldwide LHC Computing Grid (WLCG) require comprehensive simulation tools for evaluating performance, testing new algorithms, and optimizing resource allocation strategies.…

Large Language Models (LLMs) have become extremely potent instruments with exceptional capacities for comprehending and producing human-like text in a wide range of applications. However, the increasing size and complexity of LLMs present…

Machine Learning · Computer Science 2024-06-18 Yingbing Huang , Lily Jiaxin Wan , Hanchen Ye , Manvi Jha , Jinghua Wang , Yuhong Li , Xiaofan Zhang , Deming Chen

Recent advances in large language models (LLMs) have demonstrated strong performance in generating code for general-purpose programming languages. However, their potential for hardware description languages (HDLs), such as SystemVerilog,…

Hardware Architecture · Computer Science 2025-07-16 Arnav Sheth , Ivaxi Sheth , Mario Fritz

In this paper, we present the new FPGA EMUlation (FEMU), an open-source and configurable emulation framework for prototyping and evaluating TinyAI heterogeneous systems (HS). FEMU leverages the capability of system-on-chip (SoC)-based FPGAs…

Large language models (LLMs) have garnered significant attention across various research disciplines, including the wireless communication community. There have been several heated discussions on the intersection of LLMs and wireless…

Signal Processing · Electrical Eng. & Systems 2024-07-16 Yuyang Du , Hongyu Deng , Soung Chang Liew , Kexin Chen , Yulin Shao , He Chen

Distributed Machine Learning (DML) on resource-constrained edge devices holds immense potential for real-world applications. However, achieving fast convergence in DML in these heterogeneous environments remains a significant challenge.…

Distributed, Parallel, and Cluster Computing · Computer Science 2025-03-10 Advik Raj Basani , Siddharth Chaitra Vivek , Advaith Krishna , Arnab K. Paul

Customized accelerators have revolutionized modern computing by delivering substantial gains in energy efficiency and performance through hardware specialization. Field-Programmable Gate Arrays (FPGAs) play a crucial role in this paradigm,…

Hardware Architecture · Computer Science 2025-09-25 Stéphane Pouget , Michael Lo , Louis-Noël Pouchet , Jason Cong

Data movement between memory and processors is a major bottleneck in modern computing systems. The processing-in-memory (PIM) paradigm aims to alleviate this bottleneck by performing computation inside memory chips. Real PIM hardware (e.g.,…

Hardware Architecture · Computer Science 2023-10-04 Jinfan Chen , Juan Gómez-Luna , Izzat El Hajj , Yuxin Guo , Onur Mutlu

End-to-end neural networks have achieved promising performances in natural language generation (NLG). However, they are treated as black boxes and lack interpretability. To address this problem, we propose a novel framework, heterogeneous…

Computation and Language · Computer Science 2021-02-09 Yangming Li , Kaisheng Yao

We introduce a mapping framework for deep learning inference that takes advantage of predictable neural network behavior to plan both computation and communication ahead of time. The framework generates a unified stream of instructions and…

Hardware Architecture · Computer Science 2025-09-05 Md Rownak Hossain Chowdhury , Mostafizur Rahman

Requirements expressed in natural language are an indispensable artifact in the software development process, as all stakeholders can understand them. However, their ambiguity poses a persistent challenge. To address this issue,…

Software Engineering · Computer Science 2025-04-16 Mauro José Pacchiotti , Mariel Ale y Luciana Ballejos

Increasing AI computing demands and slowing transistor scaling have led to the advent of Multi-Chip-Module (MCMs) based accelerators. MCMs enable cost-effective scalability, higher yield, and modular reuse by partitioning large chips into…

Hardware Architecture · Computer Science 2025-05-06 Ritik Raj , Shengjie Lin , William Won , Tushar Krishna

Image processing algorithms are prime targets for hardware acceleration as they are commonly used in resource- and power-limited applications. Today's image processing accelerator designs make rigid assumptions about the algorithm…

Hardware Architecture · Computer Science 2023-04-10 Nisarg Ujjainkar , Jingwen Leng , Yuhao Zhu

In this paper, we propose a methodology for partitioning and mapping computational intensive applications in reconfigurable hardware blocks of different granularity. A generic hybrid reconfigurable architecture is considered so as the…

Hardware Architecture · Computer Science 2011-11-09 M. D. Galanis , A. Milidonis , G. Theodoridis , D. Soudris , C. E. Goutis

Modern computing systems increasingly rely on composing heterogeneous devices to improve performance and efficiency. Programming these systems is often unproductive: algorithm implementations must be coupled to system-specific logic,…

Programming Languages · Computer Science 2025-03-17 Russel Arbore , Aaron Councilman , Xavier Routh , Ryan Ziegler , Praneet Rathi , Vikram Adve

We introduce an approach to designing FPGA-accelerated middleboxes that simplifies development, debugging, and performance tuning by decoupling the tasks of hardware-accelerator implementation and software-application programming. Rosebud…

Hardware Architecture · Computer Science 2023-03-20 Moein Khazraee , Alex Forencich , George Papen , Alex C. Snoeren , Aaron Schulman