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The rapid development of multi-core system and increase of data-intensive application in recent years call for larger main memory. Traditional DRAM memory can increase its capacity by reducing the feature size of storage cell. Now further…
This paper introduces a novel iterative algorithm for optimizing pilot and data power control (PC) in cell-free massive multiple-input multiple-output (CF-mMIMO) systems, aiming to enhance system performance under real-time channel…
This work presents a multi-layered methodology for efficiently accelerating multimodal foundation models (MFMs). It combines hardware and software co-design of transformer blocks with an optimization pipeline that reduces computational and…
In the last decade, the demand for Internet applications has been increased, which increases the number of data centers across the world. These data centers are usually connected to each other using long-distance and high-speed networks. As…
Satisfying the stringent 5G Quality of Service (QoS) requirements necessitates efficient resource utilization by the mobile networks. Consequently, we argue that Multi-Connectivity (MC) is an effective solution to leverage the limited radio…
Hybrid MPI+threads programming is gaining prominence, but, in practice, applications perform slower with it compared to the MPI everywhere model. The most critical challenge to the parallel efficiency of MPI+threads applications is slow…
Ultra-reliable low-latency communication is essential in mission-critical settings, including military applications, where persistent and asymmetric link blockages caused by mobility, jamming, or adversarial attacks can disrupt…
Memory-centric computing aims to enable computation capability in and near all places where data is generated and stored. As such, it can greatly reduce the large negative performance and energy impact of data access and data movement, by…
Efficient radio spectrum utilization and low energy consumption in mobile devices are essential in developing next generation wireless networks. This paper presents a new medium access control (MAC) mechanism to enhance spectrum efficiency…
Predictable execution time upon accessing shared memories in multi-core real-time systems is a stringent requirement. A plethora of existing works focus on the analysis of Double Data Rate Dynamic Random Access Memories (DDR DRAMs), or…
Unlike conventional converters, modular multilevel converter (MMC) has a higher switching frequency -- which has direct implication on important parameters like converter loss and reliability -- mainly due to increased number of switching…
Bandwidth-starved multicore chips have become ubiquitous. It is well known that the performance of stencil codes can be improved by temporal blocking, lessening the pressure on the memory interface. We introduce a new pipelined approach…
Energy consumption is an important concern in modern multicore processors. The energy consumed during the execution of an application can be minimized by tuning the hardware state utilizing knobs such as frequency, voltage etc. The existing…
Modern operating systems (OSes) have unfettered access to application data, assuming that applications trust them. This assumption, however, is problematic under many scenarios where either the OS provider is not trustworthy or the OS can…
This paper aims to develop an efficient open-source Secure Multi-Party Computation (SMPC) repository, that addresses the issue of practical and scalable implementation of SMPC protocol on machines with moderate computational resources,…
Cell-free massive MIMO (CF mMIMO) is a promising next generation wireless architecture to realize federated learning (FL). However, sensitive information of user equipments (UEs) may be exposed to the involved access points or the central…
The memory system of a modern embedded processor consumes a large fraction of total system energy. We explore a range of different configuration options and show that a reconfigurable design can make better use of the resources available to…
The throughput efficiency of a wireless mesh network with potentially malicious external or internal interference can be significantly improved by equipping routers with multi-radio access over multiple channels. For reliably mitigating the…
Memory controller scheduling is crucial in multicore processors, where DRAM bandwidth is shared. Since increased number of requests from multiple cores of processors becomes a source of bottleneck, scheduling the requests efficiently is…
High-speed signal processing is essential for maximizing data throughput in emerging communication applications, like multiple-input multiple-output (MIMO) systems and radio-frequency (RF) interference cancellation. However, as these…