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Putting the DRAM on the same package with a processor enables several times higher memory bandwidth than conventional off-package DRAM. Yet, the latency of in-package DRAM is not appreciably lower than that of off-package DRAM. A promising…

Hardware Architecture · Computer Science 2017-04-11 Xiangyao Yu , Christopher J. Hughes , Nadathur Satish , Onur Mutlu , Srinivas Devadas

Many virtual machines exist for sensor nodes with only a few KB RAM and tens to a few hundred KB flash memory. They pack an impressive set of features, but suffer from a slowdown of one to two orders of magnitude compared to optimised…

Programming Languages · Computer Science 2017-12-19 Niels Reijers , Chi-Sheng Shih

Flash memory devices are winning the competition for storage density against magnetic recording devices. This outcome results from advances in physics that allow storage of more than one bit per cell, coupled with advances in signal…

Information Theory · Computer Science 2020-12-09 Ahmed Hareedy , Beyza Dabak , Robert Calderbank

Index structures are important for efficient data access, which have been widely used to improve the performance in many in-memory systems. Due to high in-memory overheads, traditional index structures become difficult to process the…

Databases · Computer Science 2019-05-16 Pengfei Li , Yu Hua , Pengfei Zuo , Jingnan Jia

Read-optimized columnar databases use differential updates to handle writes by maintaining a separate write-optimized delta partition which is periodically merged with the read-optimized and compressed main partition. This merge process…

The pivotal storage density win achieved by solid-state devices over magnetic devices in 2015 is a result of multiple innovations in physics, architecture, and signal processing. One of the most important innovations in that regard is…

Information Theory · Computer Science 2022-09-07 Ahmed Hareedy , Simeng Zheng , Paul Siegel , Robert Calderbank

Modern caches are often required to handle a massive amount of data, which exceeds the amount of available memory; thus, hybrid caches, specifically DRAM/SSD combination, become more and more prevalent. In such environments, in addition to…

Operating Systems · Computer Science 2022-06-28 Ohad Eytan , Roy Friedman

With more devices connected, delays and jitter at the WiFi hop become more prevalent, and correct functioning during network congestion becomes more important. However, two important performance issues prevent modern WiFi from reaching its…

Networking and Internet Architecture · Computer Science 2017-03-07 Toke Høiland-Jørgensen , Michał Kazior , Dave Täht , Per Hurtig , Anna Brunstrom

Multi-core processors improve performance, but they can create unpredictability owing to shared resources such as caches interfering. Cache partitioning is used to alleviate the Worst-Case Execution Time (WCET) estimation by isolating the…

Hardware Architecture · Computer Science 2022-01-28 Soma N. Ghosh , Vineet Sahula , Lava Bhargava

A recent discovery of a new class of microarchitectural attacks called Spectre picked up the attention of the security community as these attacks can circumvent many traditional mechanisms of defense. One of the attacks---Bounds Check…

Cryptography and Security · Computer Science 2018-10-11 Oleksii Oleksenko , Bohdan Trach , Tobias Reiher , Mark Silberstein , Christof Fetzer

In the online packet buffering problem (also known as the unweighted FIFO variant of buffer management), we focus on a single network packet switching device with several input ports and one output port. This device forwards unit-size,…

Data Structures and Algorithms · Computer Science 2012-08-15 Marcin Bienkowski

Cache partitioning techniques have been successfully adopted to mitigate interference among concurrently executing real-time tasks on multi-core processors. Considering that the execution time of a cache-sensitive task strongly depends on…

Hardware Architecture · Computer Science 2023-10-05 Binqi Sun , Debayan Roy , Tomasz Kloda , Andrea Bastoni , Rodolfo Pellizzoni , Marco Caccamo

Efficient virtualization of CPU and memory is standardized and mature. Capabilities such as Intel VT-x [3] have been added by manufacturers for efficient hypervisor support. In contrast, virtualization of a block device and its presentation…

Networking and Internet Architecture · Computer Science 2024-09-05 Vojtech Aschenbrenner , John Shawger , Sadman Sakib

Storage systems have not kept the same technology improvement rate as computing systems. As applications produce more and more data, I/O becomes the limiting factor for increasing application performance. I/O congestion caused by concurrent…

Distributed, Parallel, and Cluster Computing · Computer Science 2021-11-03 Hatem Elshazly , Jorge Ejarque , Francesc Lordan , Rosa M. Badia

Host-side page victimizations can easily overflow the SSD internal buffer, which interferes I/O services of diverse user applications thereby degrading user-level experiences. To address this, we propose FastDrain, a co-design of OS kernel…

Operating Systems · Computer Science 2020-06-23 Jie Zhang , Miryeong Kwon , Sanghyun Han , Nam Sung Kim , Mahmut Kandemir , Myoungsoo Jung

Containers have become a standard for deploying applications due to their convenience, but they often suffer from significant software bloat-unused files that inflate image sizes, increase provisioning times, and waste resources. These…

Software Engineering · Computer Science 2025-02-20 Huaifeng Zhang , Mohannad Alhanahnah , Philipp Leitner , Ahmed Ali-Eldin

Current generation solid-state storage devices are exposing a new bottlenecks in the SCSI and block layers of the Linux kernel, where IO throughput is limited by lock contention, inefficient interrupt handling, and poor memory locality. To…

Operating Systems · Computer Science 2015-04-29 Blake Caldwell

In-memory data management systems, such as key-value stores, have become an essential infrastructure in today's big-data processing and cloud computing. They rely on efficient index structures to access data. While unordered indexes, such…

Databases · Computer Science 2019-02-19 Xingbo Wu , Fan Ni , Song Jiang

To accommodate the needs of large-scale distributed P2P systems, scalable data management strategies are required, allowing applications to efficiently cope with continuously growing, highly dis tributed data. This paper addresses the…

Distributed, Parallel, and Cluster Computing · Computer Science 2009-09-30 Bogdan Nicolae , Gabriel Antoniu , Luc Bougé

Fence instructions are fundamental primitives that ensure consistency in a weakly consistent shared memory multi-core processor. The execution cost of these instructions is significant and adds a non-trivial overhead to parallel programs.…

Hardware Architecture · Computer Science 2017-12-07 Pranith Kumar , Prasun Gera , Hyojong Kim , Hyesoon Kim
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