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Quantum error correction (QEC) is a cornerstone of quantum computing, enabling reliable information processing in the presence of noise. Sparse stabilizer codes -- referred to generally as quantum low-density parity-check (QLDPC) codes --…

Quantum Physics · Physics 2025-10-20 Bane Vasic , Valentin Savin , Michele Pacenti , Shantom Borah , Nithin Raveendran

We present a fault-tolerant universal quantum computing architecture based on a code concatenation of biased-noise qubits and the parity architecture. The parity architecture can be understood as an LDPC code tailored specifically to obtain…

Quantum Physics · Physics 2025-12-01 Anette Messinger , Valentin Torggler , Berend Klaver , Michael Fellner , Wolfgang Lechner

To well understand the behavior of quantum error correction codes (QECC) in noise processes, we need to obtain explicit coding maps for QECC. Due to extraordinary amount of computational labor that they entails, explicit coding maps are a…

Quantum Physics · Physics 2022-03-04 Chaobin Liu

Quantum error correction is an indispensable ingredient for scalable quantum computing. In this Perspective we discuss a particular class of quantum codes called low-density parity-check (LDPC) quantum codes. The codes we discuss are…

Quantum Physics · Physics 2021-10-26 Nikolas P. Breuckmann , Jens Niklas Eberhardt

In this paper, we consider how to partition the parity-check matrices (PCMs) to reduce the hardware complexity and computation delay for the row layered decoding of quasi-cyclic low-density parity-check (QC-LDPC) codes. First, we formulate…

Information Theory · Computer Science 2022-08-30 Teng Lu , Xuan He , Peng Kang , Jiongyue Xing , Xiaohu Tang

It is widely accepted that quantum error correction is essential for realizing large-scale fault-tolerant quantum computing. Recent experiments have demonstrated error correction codes operating below threshold, primarily using local planar…

Quantum Physics · Physics 2026-01-21 Christian Kraglund Andersen , Eliška Greplová

As quantum computing moves toward fault-tolerant architectures, quantum error correction (QEC) decoder performance is increasingly critical for scalability. Understanding the impact of transitioning from floating-point software to…

Quantum Physics · Physics 2026-04-22 Francisco Garcia-Herrero , Javier Valls , Llanos Vergara-Picazo , Vicente Torres

Utility-scale quantum computing requires quantum error correction (QEC) to protect quantum information against noise. Currently, superconducting hardware is a promising candidate for achieving fault tolerance due to its fast gate times and…

Quantum Physics · Physics 2025-08-06 György P. Gehér , David Byfield , Archibald Ruban

Quantum Error Correction (QEC) is an essential field of research towards the realization of large-scale quantum computers. On the theoretical side, a lot of effort is put into designing error-correcting codes that protect quantum data from…

Quantum Physics · Physics 2023-02-10 Lucas Berent , Lukas Burgholzer , Robert Wille

A major challenge in fault-tolerant quantum computation (FTQC) is to reduce both space overhead -- the large number of physical qubits per logical qubit -- and time overhead -- the long physical gate sequences per logical gate. We prove…

Quantum Physics · Physics 2024-12-06 Shiro Tamiya , Masato Koashi , Hayata Yamasaki

Scaling up quantum computers to attain substantial speedups over classical computing requires fault tolerance. Conventionally, protocols for fault-tolerant quantum computation demand excessive space overheads by using many physical qubits…

Quantum Physics · Physics 2025-01-29 Hayata Yamasaki , Masato Koashi

Vast numbers of qubits will be needed for large-scale quantum computing due to the overheads associated with error correction. We present a scheme for low-overhead fault-tolerant quantum computation based on quantum low-density parity-check…

Quantum Physics · Physics 2022-05-24 Lawrence Z. Cohen , Isaac H. Kim , Stephen D. Bartlett , Benjamin J. Brown

Quantum error correction is an essential ingredient for universal quantum computing. Despite tremendous experimental efforts in the study of quantum error correction, to date, there has been no demonstration in the realisation of universal…

Fault tolerant quantum computers will require efficient co-processors for real-time decoding of their adopted quantum error correction protocols. In this work we examine the possibility of using specialised Ising model hardware to perform…

Quantum Physics · Physics 2019-03-26 Joschka Roffe , Stefan Zohren , Dominic Horsman , Nicholas Chancellor

Error correcting codes use multi-qubit measurements to realize fault-tolerant quantum logic steps. In fact, the resources needed to scale-up fault-tolerant quantum computing hardware are largely set by this task. Tailoring next-generation…

Quantum error correction (QEC) is believed to be essential for the realization of large-scale quantum computers. However, due to the complexity of operating on the encoded `logical' qubits, understanding the physical principles for building…

Logical qubits can be protected from decoherence by performing QEC cycles repeatedly. Algorithms for fault-tolerant QEC must be compiled to the specific hardware platform under consideration in order to practically realize a quantum memory…

Quantum Physics · Physics 2025-05-13 Sascha Heußen , David F. Locher , Markus Müller

Methods of finding good quantum error correcting codes are discussed, and many example codes are presented. The recipe C_2^{\perp} \subseteq C_1, where C_1 and C_2 are classical codes, is used to obtain codes for up to 16 information qubits…

Quantum Physics · Physics 2008-12-18 Andrew Steane

The realization of quantum error correction protocols whose logical error rates are suppressed far below physical error rates relies on an intricate combination: the error-correcting code's efficiency, the syndrome extraction circuit's…

Quantum Physics · Physics 2026-03-06 Andrey Boris Khesin , Jonathan Z. Lu

Chip Guard is a new approach to symbol-correcting error correction codes. It can be scaled to various data burst sizes and reliability levels. A specific version for DDR5 is described. It uses the usual DDR5 configuration of 8 data chips,…

Hardware Architecture · Computer Science 2023-01-19 Tanj Bennett