Related papers: Computing via material topology optimisation
This thesis proposes novel ternary circuits aiming to reduce energy to preserve battery consumption. The proposed designs include eight ternary logic gates, three ternary combinational circuits, and six Ternary Arithmetic Logic Units. This…
The ambition constrained validity and the model witness problems in the logic UCL, for reasoning about circuits with unreliable gates, are analyzed. Moreover, two additional problems, motivated by the applications, are studied. One consists…
In this study, we describe a procedure of topology optimization in the framework of the linear Boltzmann equation, implemented using a reference Monte-Carlo particle transport code. This procedure can design complex structures that optimize…
In the paper electromagnetic signals distinguished by their discrete modulation of spatial distributions of fields and amplitudes are considered. Amplitudes of the impulses play a role of predicates and discrete spatial distributions of…
Atomic-scale logic and the minimization of heating (dissipation) are both very high on the agenda for future computation hardware. An approach to achieve these would be to replace networks of transistors directly by classical reversible…
This paper presents arithmetic operations like addition, subtraction and multiplications in Modulo-4 arithmetic, and also addition, multiplication in Galois field, using multi-valued logic (MVL). Quaternary to binary and binary to…
Robust gate sequences are widely used to reduce the sensitivity of gate operations to experimental imperfections. Typically, the optimization minimizes the average gate error, however, recent work in quantum error correction has…
In this paper we present the core of LoCo, a logic-based high-level representation language for expressing configuration problems. LoCo shall allow to model these problems in an intuitive and declarative way, the dynamic aspects of…
The emergence of large reasoning models demonstrates that scaling inference-time compute significantly enhances performance on complex tasks. However, it often falls into another trap: overthinking simple problems, where repetitive…
The anyonic excitations of topological two-body color code model are used to implement a set of gates. Because of two-body interactions, the model can be simulated in optical lattices. The excitations have nontrivial mutual statistics, and…
Memcomputing logic gates generalize the traditional Boolean logic gates for operation in the reverse direction. According to the literature, this functionality enables the efficient solution of computationally-intensive problems including…
Robust topology optimization (RTO), as a class of topology optimization problems, identifies a design with the best average performance while reducing the response sensitivity to input uncertainties, e.g. load uncertainty. Solving RTO is…
With recent advances in both responsive materials and fabrication techniques it is now possible to construct integrated functional structures, composed of both structural and active materials. We investigate the robust design of such…
Construction of parallel logic gates at nano-scale level undoubtedly improves the efficiency of computable operations. In this work we put forward a new idea of designing two distinct logical operations {\em simultaneously} in the two…
Holonomic quantum computation makes use of non-abelian geometric phases, associated to the evolution of a subspace of quantum states, to encode logical gates. We identify a special class of subspaces, for which a sequence of rotations…
For all-optical communication and information processing, it is necessary to develop all-optical logic gates based on photonic structures that can directly perform logic operations. All-optical logic gates have been demonstrated based on…
Optimization problems that involve topology optimization in scenarios with large scale outages, such as post-disaster restoration or public safety power shutoff planning, are very challenging to solve. Using simple power flow…
quest for processing speed potential. In fact, we always get a fraction of the technically available computing power (so-called {\em theoretical peak}), and the gap is likely to go hand-to-hand with the hardware complexity of the target…
We introduce a novel logic style with self-checking capability to enhance hardware reliability at logic level. The proposed logic cells have two-rail inputs/outputs, and the functionality for each rail of outputs enables construction of…
Efficient thermal management in high-power electronic devices requires cooling channel designs that provide high heat removal while satisfying strict spatial and manufacturing constraints. This study presents a two-stage hierarchical…