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Hardware faults on the regular 2-D computing array of a typical deep learning accelerator (DLA) can lead to dramatic prediction accuracy loss. Prior redundancy design approaches typically have each homogeneous redundant processing element…

Neuroevolution is a powerful method of applying an evolutionary algorithm to refine the performance of artificial neural networks through natural selection; however, the fitness evaluation of these networks can be time-consuming and…

Massively parallel architectures offer the potential to significantly accelerate an application relative to their serial counterparts. However, not all applications exhibit an adequate level of data and/or task parallelism to exploit such…

In this paper, we propose TAPA, an end-to-end framework that compiles a C++ task-parallel dataflow program into a high-frequency FPGA accelerator. Compared to existing solutions, TAPA has two major advantages. First, TAPA provides a set of…

Many important problems in Bioinformatics (e.g., assembly or multi-assembly) admit multiple solutions, while the final objective is to report only one. A common approach to deal with this uncertainty is finding safe partial solutions (e.g.,…

Flow-based microfluidic biochips are widely used in lab- on-a-chip experiments. In these chips, devices such as mixers and detectors connected by micro-channels execute specific operations. Intermediate fluid samples are saved in storage…

Inexpensive, portable lab-on-a-chip devices would revolutionize fields like environmental monitoring and global health, but current microfluidic chips are tethered to extensive off-chip hardware. Insects, however, are self-contained and…

[First paragraph] In a recent paper Yamada et al. propose the novel concept of "pinched flow fractionation" (PFF) for the continuous size separation and analysis of particles in microfabricated lab-on-a-chip devices. In their description of…

Compressive focal plane arrays (FPA) enable cost-effective high-resolution (HR) imaging by acquisition of several multiplexed measurements on a low-resolution (LR) sensor. Multiplexed encoding of the visual scene is typically performed via…

We present a new way to construct analytical solutions for flow in complex microfluidic channel networks, as well as planar disordered media. Using a combination of Schwarz-Christoffel maps and segmentation techniques inspired by integrated…

Even though it seems that FPGAs have finally made the transition from research labs to the consumer devices' market, programming them remains challenging. Despite the improvements made by High-Level Synthesis (HLS), which removed the…

In this study, we present a parallel topology algorithm with a suitable interpolation method for chimera simulations in CFD. The implementation is done in the unstructured Finite Volume (FV) framework and special attention is given to the…

Transformer-based models have shown strong performance across diverse time-series tasks, but their deployment on resource-constrained devices remains challenging due to high memory and computational demand. While prior work targeting…

The advances in fabrication processes in different material platforms employed in integrated optics are opening the path towards the implementation of circuits with increasing degree of complexity. In addition to the more conventional…

The concept and synthesis approach for planar Compliant Fluidic Control Structures (CFCSs), monolithic flexible continua with embedded functional pores, is presented in this manuscript. Such structures are envisioned to find application in…

Most neural network designs for FPGAs are inflexible. In this paper, we propose a flexible VHDL structure that would allow any neural network to be implemented on multiple FPGAs. Moreover, the VHDL structure allows for testing as well as…

This paper presents an innovative approach to micro-phasor measurement unit (micro-PMU) placement in unbalanced distribution networks. The methodology accounts for the presence of single-and-two-phase laterals and acknowledges the fact that…

In the context of various application scenarios and/or for the sake of strengthening field-programmable gate array (FPGA) security, the system functions of an FPGA design need to be analyzed, which can be achieved by systematically…

Implementing convolutional neural networks (CNNs) on field-programmable gate arrays (FPGAs) has emerged as a promising alternative to GPUs, offering lower latency, greater power efficiency and greater flexibility. However, this development…

Ising Machine is a promising computing approach for solving combinatorial optimization problems. It is naturally suited for energy-saving and compact in-memory computing implementations with emerging memories. A na\"ive in-memory computing…