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We focus on the commonly used synchronous Gradient Descent paradigm for large-scale distributed learning, for which there has been a growing interest to develop efficient and robust gradient aggregation strategies that overcome two key…
This paper is concerned with the design of capacity approaching ensembles of Low-Densiy Parity-Check (LDPC) codes for correlated sources. We consider correlated binary sources where the data is encoded independently at each source through a…
Demand for on-chip low-dropout regulators (LDOs) with both high power-supply rejection ratio (PSRR) and fast transient response is growing as system-on-chip (SoC) integration increases. However, conventional LDO architectures face…
Binary multipliers have long been a staple component in digital circuitry, serving crucial roles in microprocessor design, digital signal processing units and many more applications. This work presents a unique design for a multiplier that…
High-rate and large-distance quantum codes are expected to make fault-tolerant quantum computing more efficient, but most of them lack efficient fault-tolerant encoded-state preparation methods. We propose such a fault-tolerant encoder for…
Dynamic data race detectors are indispensable for flagging concurrency errors in software, but their high runtime overhead limits their adoption. This overhead stems primarily from pervasive instrumentation of memory accesses - a…
Fully Homomorphic Encryption (FHE) enables privacy-preserving computation and has many applications. However, its practical implementation faces massive computation and memory overheads. To address this bottleneck, several…
In the field of cryptography till date the 1-byte in 1-clock is the best known RC4 hardware design [1], while the 1-byte in 3clocks is the best known implementation [2,3]. The design algorithm in [1] considers two consecutive bytes together…
In the field of cryptography till date the 2-byte in 1-clock is the best known RC4 hardware design [1], while 1-byte in 1-clock [2], and the 1-byte in 3 clocks [3][4] are the best known implementation. The design algorithm in[2] considers…
Many information systems employ lossy compression as a crucial intermediate stage among other processing components. While the important distortion is defined by the system's input and output signals, the compression usually ignores the…
Time-to-Digital Converters (TDCs) are major components for the measurements of time intervals. Recent developments in Field-Programmable Gate Array (FPGA) have enabled the opportunity to implement high-performance TDCs, which were only…
In the era of diminishing returns from Moores Law, heterogeneous computing systems have emerged as a vital approach to enhance computational efficiency. This paper introduces a novel MLIR-based dialect, named hyper, designed to optimize…
Quantum-dot Cellular Automata (QCA) is one of the emerging nanotechnologies, promising alternative to CMOS technology due to faster speed, smaller size, lower power consumption, higher scale integration and higher switching frequency. Also,…
We consider the problem of constructing fast and small binary adder circuits. Among widely-used adders, the Kogge-Stone adder is often considered the fastest, because it computes the carry bits for two $n$-bit numbers (where $n$ is a power…
Most of today's communication systems are designed to target reliable message recovery after receiving the entire encoded message (codeword). However, in many practical scenarios, the transmission process may be interrupted before receiving…
Quantum error correction is necessary to perform large-scale quantum computation, but requires extremely large overheads in both space and time. High-rate quantum low-density-parity-check (qLDPC) codes promise a route to reduce qubit…
In this paper, we propose and evaluate two novel double-sequence low-resolution frequency synchronization methods in millimeter-wave (mmWave) systems. In our system model, the base station uses analog beams to send the synchronization…
In this paper, we investigate a novel reconfigurable distributed antennas and reflecting surface (RDARS) aided multi-user massive MIMO system with imperfect CSI and propose a practical two-timescale (TTS) transceiver design to reduce the…
We consider the downlink of a massive multiuser (MU) multiple-input multiple-output (MIMO) system in which the base station (BS) is equipped with low-resolution digital-to-analog converters (DACs). In contrast to most existing results, we…
We propose a method to impose homogeneous linear inequality constraints of the form $Ax\leq 0$ on neural network activations. The proposed method allows a data-driven training approach to be combined with modeling prior knowledge about the…