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Data transfers are essential in today's computing systems as latency and complex memory access patterns are increasingly challenging to manage. Direct memory access engines (DMAEs) are critically needed to transfer data independently of the…

Coded caching is an emerging technique to reduce the data transmission load during the peak-traffic times. In such a scheme, each file in the data center or library is usually divided into a number of packets to pursue a low broadcasting…

Information Theory · Computer Science 2022-01-06 Xianzhang Wu , Minquan Cheng , Congduan Li , Li Chen

Deep Neural Networks (DNNs) have become an essential component in many application domains including web-based services. A variety of these services require high throughput and (close to) real-time features, for instance, to respond or…

Machine Learning · Computer Science 2022-09-20 Mohammadamin Abedi , Yanni Iouannou , Pooyan Jamshidi , Hadi Hemmati

Edge computing and IoT applications are severely constrained by limited hardware resource. This makes memory consuming DNN frameworks not applicable to edge computing. Simple algorithms such as direct convolution are finding their way in…

Distributed, Parallel, and Cluster Computing · Computer Science 2019-10-17 Xianwei Cheng , Hui Zhao , Mahmut Kandemir , Saraju Mohanty , Beilei Jiang

This paper summarizes the idea of Adaptive-Latency DRAM (AL-DRAM), which was published in HPCA 2015, and examines the work's significance and future potential. AL-DRAM is a mechanism that optimizes DRAM latency based on the DRAM module and…

Hardware Architecture · Computer Science 2018-05-09 Donghyuk Lee , Yoongu Kim , Gennady Pekhimenko , Samira Khan , Vivek Seshadri , Kevin Chang , Onur Mutlu

Intel OptaneTM DC Persistent Memory resides on the memory bus and approaches DRAM in access latency. One avenue for its adoption is to employ it in place of persistent storage; another is to use it as a cheaper and denser extension of DRAM.…

Hardware Architecture · Computer Science 2022-05-30 Alexandra Fedorova , Keith Smith , Keith Bostic , Alexander Gorrod , Sue LoVerso , Michael Cahill

The speed of modern digital systems is severely limited by memory latency (the ``Memory Wall'' problem). Data exchange between Logic and Memory is also responsible for a large part of the system energy consumption. Logic--In--Memory (LiM)…

Hardware Architecture · Computer Science 2023-04-14 Fabrizio Ottati , Giovanna Turvani , Marco Vacca , Guido Masera

Conventional cache models are not suited for real-time parallel processing because tasks may flush each other's data out of the cache in an unpredictable manner. In this way the system is not compositional so the overall performance is…

Hardware Architecture · Computer Science 2011-11-09 A. M. Molnos , M. J. M. Heijligers , S. D. Cotofana , J. T. J. Van Eijndhoven

Modern NVMM is closing the gap between DRAM and persistent storage, both in terms of performance and features. Having both byte addressability and persistence on the same device gives NVMM an unprecedented set of features, leading to the…

Operating Systems · Computer Science 2023-05-04 Rémi Dulong , Quentin Acher , Baptiste Lepers , Valerio Schiavoni , Pascal Felber , Gaël Thomas

Flash-based disk caches, for example Bcache and Flashcache, has gained tremendous popularity in industry in the last decade because of its low energy consumption, non-volatile nature and high I/O speed. But these cache systems have a worse…

Operating Systems · Computer Science 2023-11-16 Chaos Dong , Fang Wang , Jianshun Zhang

Memory bandwidth regulation and cache partitioning are widely used techniques for achieving predictable timing in real-time computing systems. Combined with partitioned scheduling, these methods require careful co-allocation of tasks and…

Optimization and Control · Mathematics 2025-05-20 Binqi Sun , Zhihang Wei , Andrea Bastoni , Debayan Roy , Mirco Theile , Tomasz Kloda , Rodolfo Pellizzoni , Marco Caccamo

Modern DRAM modules are often equipped with hardware error correction capabilities, especially for DRAM deployed in large-scale data centers, as process technology scaling has increased the susceptibility of these devices to errors. To…

Hardware Architecture · Computer Science 2017-06-29 Yixin Luo , Saugata Ghose , Tianshi Li , Sriram Govindan , Bikash Sharma , Bryan Kelly , Amirali Boroumand , Onur Mutlu

Prime generation is a fundamental task in cryptography, number theory, and randomized algorithms. While the classical Sieve of Eratosthenes is simple and efficient in theory, its practical performance on modern central processing units is…

Data Structures and Algorithms · Computer Science 2026-01-29 Kathi Lakshmi Mani Thirdhana

On-device learning allows AI models to adapt to user data, thereby enhancing service quality on edge platforms. However, training AI on resource-limited devices poses significant challenges due to the demanding computing workload and the…

Hardware Architecture · Computer Science 2023-12-27 Sai Qian Zhang , Thierry Tambe , Nestor Cuevas , Gu-Yeon Wei , David Brooks

With the advent of 5G networks and the rise of the Internet of Things (IoT), Content Delivery Networks (CDNs) are increasingly extending into the network edge. This shift introduces unique challenges, particularly due to the limited cache…

Networking and Internet Architecture · Computer Science 2024-04-05 Hoda Torabi , Hamzeh Khazaei , Marin Litoiu

Persistent Memory (PM) is a new storage technology thatbrings high performance, byte addressability, and persistency for a lesser cost than DRAM. Due to cache volatility and store reordering, developers must use explicit instructions (e.g.:…

Emerging Technologies · Computer Science 2026-03-03 Sebastião Amaro , João Gonçalves , Miguel Matos

Memory bandwidth bottleneck is a major challenges in processing machine learning (ML) algorithms. In-memory acceleration has potential to address this problem; however, it needs to address two challenges. First, in-memory accelerator should…

Machine Learning · Computer Science 2019-01-10 Hajar Falahati , Pejman Lotfi-Kamran , Mohammad Sadrosadati , Hamid Sarbazi-Azad

Three-dimensional (3D)-stacking technology, which enables the integration of DRAM and logic dies, offers high bandwidth and low energy consumption. This technology also empowers new memory designs for executing tasks not traditionally…

Hardware Architecture · Computer Science 2018-12-05 Ramyad Hadidi , Bahar Asgari , Burhan Ahmad Mudassar , Saibal Mukhopadhyay , Sudhakar Yalamanchili , Hyesoon Kim

The deep neural network (DNN) based AI applications on the edge require both low-cost computing platforms and high-quality services. However, the limited memory, computing resources, and power budget of the edge devices constrain the…

Machine Learning · Computer Science 2021-05-14 Yao Chen , Cole Hawkins , Kaiqi Zhang , Zheng Zhang , Cong Hao

The importance of intelligent data placement, management, and analysis has become apparent as scientific data volumes across the network continue to increase. To that end, we describe the use of in-network caching service deployments as a…

Networking and Internet Architecture · Computer Science 2022-03-15 Alex Sim , Ezra Kissel , Chin Guok
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