Related papers: Analysis and Design of a Passive Switched-Capacito…
Analog compute-in-memory (CIM) in static random-access memory (SRAM) is promising for accelerating deep learning inference by circumventing the memory wall and exploiting ultra-efficient analog low-precision arithmetic. Latest analog CIM…
Edge computing is emerging as a new paradigm to allow processing data at the edge of the network, where data is typically generated and collected, by exploiting multiple devices at the edge collectively. However, exploiting the potential of…
We propose an optimization method for the automatic design of approximate multipliers, which minimizes the average error according to the operand distributions. Our multiplier achieves up to 50.24% higher accuracy than the best reproduced…
The purpose of this project was to design and implement a pipeline Analog-to-Digital Converter using 0.35um CMOS technology. Initial requirements of a 25-MHz conversion rate and 8-bits of resolution where the only given ones. Although…
The energy efficiency of analog computing-in-memory (ACIM) accelerator for recurrent neural networks, particularly long short-term memory (LSTM) network, is limited by the high proportion of nonlinear (NL) operations typically executed…
Superconducting qubits are a leading platform for scalable quantum computing and quantum error correction. One feature of this platform is the ability to perform projective measurements orders of magnitude more quickly than qubit…
In this work, we explore an energy-efficient implementation of the polyphase network for a filter bank multicarrier (FBMC) system. The network is approximated using a greedy algorithm based on matching pursuits (MP) that converts the…
This paper demonstrates a probabilistic bit physics inspired solver with 440 spins configured in a Chimera graph, occupying an area of 0.44 mm^2. Area efficiency is maximized through a current-mode implementation of the neuron update…
Optical computing is emerging as a promising platform for energy-efficient, high-throughput hardware in deep learning. A key challenge lies in the realization of optical matrix-vector multiplication, which often requires $O(N^2)$ phase…
High data rates require vast bandwidths, that can be found in the sub-THz band, and high sampling frequencies, which are predicted to lead to a problematically high analog-to-digital converter (ADC) power consumption. It was proposed to use…
High power consumption and expensive hardware are two bottlenecks for practical massive multiple-input multiple-output (mMIMO) systems. One promising solution is to employ low-resolution analog-to-digital converters (ADCs) and…
Probabilistic computers built from p-bits offer a promising path for combinatorial optimization, but the dense connectivity required by real-world problems scales poorly in hardware. Here, we address this through graph sparsification with…
Within the ATTRACT FASTPIX project, a monolithic pixel sensor demonstrator chip has been developed in a modified 180 nm CMOS imaging process technology, targeting sub-nanosecond timing precision for single ionising particles. It features a…
In a high-speed coherent optical transmission system, typically the signals obtained at the receiver front-end are digitized using very high-speed ADCs and then processed in the digital domain to remove optical channel impairments. In this…
Performing data-intensive tasks in the von Neumann architecture is challenging to achieve both high performance and power efficiency due to the memory wall bottleneck. Computing-in-memory (CiM) is a promising mitigation approach by enabling…
Sparse Matrix-Matrix multiplication is a key kernel that has applications in several domains such as scientific computing and graph analysis. Several algorithms have been studied in the past for this foundational kernel. In this paper, we…
The data transfer between a processor and memory has become a design bottleneck in data-intensive applications. Processing-In-Memory (PIM) is a practical approach to overcome the memory wall bottleneck. The 4:2 compressor is suitable for…
We present an efficient numerical technique to evaluate the matrix of the (quasiparticle)-random-phase approximation, using the finite amplitude method (FAM). The method is tested in calculation of monopole excitations in 120Sn, compared…
High-speed signal processing is essential for maximizing data throughput in emerging communication applications, like multiple-input multiple-output (MIMO) systems and radio-frequency (RF) interference cancellation. However, as these…
This paper presents a switch-type attenuator working from 20 to 100 GHz. The attenuator adopts a capacitive compensation technique to reduce phase error. The small resistors in this work are implemented with metal lines to reduce the…