Related papers: Optimization on fixed low latency implementation o…
The ATLAS detector is set to undergo a substantial upgrade termed the "Phase-II" upgrade during the Long-Shutdown in preparation for the start of operation of the High Luminosity Large Hadron Collider (HL-LHC). This paper describes the…
Results of porting parts of the Lattice Quantum Chromodynamics code to modern FPGA devices are presented. A single-node, double precision implementation of the Conjugate Gradient algorithm is used to invert numerically the Dirac-Wilson…
General matrix/matrix multiplication (GEMM) is crucial for scientific computing and machine learning. However, the increased scale of the computing platforms raises concerns about hardware and software reliability. In this poster, we…
The ATLAS detector at CERN's Large Hadron Collider (LHC) will be exposed to proton-proton collisions from beams crossing at 40 MHz. At the design luminosity of 10^34 cm^-2 s^-1 there are on average 23 collisions per bunch crossing. A…
The objective of this paper is to design and implement an intelligent Traffic Light Controller system for a four way road intersection. The design is carried out using Verilog, and the hardware is implemented on a FPGA. The chosen…
Fluid antenna systems (FAS) exploit antenna position reconfigurability to unlock massive spatial diversity within compact form factors, making them a promising enabler for 6G user terminals (UTs). However, practical port switching incurs…
A new module concept for future ATLAS pixel detector upgrades is presented, where thin n-in-p silicon sensors are connected to the front-end chip exploiting the novel Solid Liquid Interdiffusion technique (SLID) and the signals are read out…
The High-Granularity Timing Detector is a detector proposed for the ATLAS Phase II upgrade. The detector, based on the Low-Gain Avalanche Detector (LGAD) technology will cover the pseudo-rapidity region of $2.4<|\eta|<4.0$ with two end caps…
Recent advancements in large language models (LLMs) boasting billions of parameters have generated a significant demand for efficient deployment in inference workloads. The majority of existing approaches rely on temporal architectures that…
To meet the demands of the Beam Energy Scan phase-II (BES-II) program, the STAR experiment at RHIC developed a dual real-time framework consisting of a High Level Trigger (HLT) and an Express Data Production system (xProduction). The HLT…
ALICE is a general purpose experiment dedicated to the study of nucleus-nucleus collisions at LHC. After more than 3 years of successful operation, an upgrade of the apparatus during the second long shutdown of LHC (LS2) in 2017/18 is in…
Graph Neural Networks (GNNs), particularly Interaction Networks (INs), have shown exceptional performance for jet tagging at the CERN High-Luminosity Large Hadron Collider (HL-LHC). However, their computational complexity and irregular…
We present an R&D activity focused on the development of novel modules for the upgrade of the ATLAS pixel system at the High Luminosity LHC (HL-LHC). The modules consist of n-in-p pixel sensors, 100 or 200 $\mu$m thick, produced at VTT…
Present state of the art applications in the area of high energy physics experiments (HEP), radar communication, satellite communication and bio medical instrumentation require fault resilient data acquisition (DAQ) system with the data…
First Experiences Integrating PC Distributed I/O Into Argonne's ATLAS Control System The roots of ATLAS (Argonne Tandem-Linac Accelerator System) date back to the early 1960s. Located at the Argonne National Laboratory, the accelerator has…
LUT (Look-Up Table) mapping is a critical step in FPGA logic synthesis, where a logic network is transformed into a form that can be directly implemented using the FPGA's LUTs. An FPGA LUT is a flexible digital memory structure that can…
This paper presents a novel gradient compression method for federated learning (FL) in wireless systems. The proposed method centers on a low-rank matrix factorization strategy for local gradient compression that is based on one iteration…
The ATLAS detector is installed in its experimental cavern at Point 1 of the CERN Large Hadron Collider. During Run 2 of the LHC, a luminosity of $\mathcal{L}=2\times 10^{34}\mathrm{cm}^{-2}\mathrm{s}^{-1}$ was routinely achieved at the…
The ATLAS detector at CERN's Large Hadron Collider will be exposed to proton-proton collisions from beams crossing at 40 MHz that have to be reduced to the few 100 Hz allowed by the storage systems. A three-level trigger system has been…
Most FPGA boards in the HPC domain are well-suited for parallel scaling because of the direct integration of versatile and high-throughput network ports. However, the utilization of their network capabilities is often challenging and…