Related papers: A Modular Data Acquisition System using the 10 GSa…

A 20 GHz LLRF system is being built using a two-board(RF Front End + ADC/DAC/FPGA) architecture. The RF Front End provides 8 down-converting channels and 3 up-converting channels (5.5-20 GHz RF to 0.05-3 GHz IF). Separate, phase locked,…

We present the ARAGORN front-end, a cost-optimized, high-density Time-to-Digital Converter platform. Four Xilinx Artix-7 FPGAs implement 384 channels with an average time resolution of 165 ps on a single module. A fifth FPGA acts as data…

The integration of compressive sensing with real-time embedded systems opens new possibilities for efficient, low-power biomedical signal acquisition. This paper presents a custom hardware platform based on the RP2350 micro-controller,…

Power side-channel analysis (SCA) has been of immense interest to most embedded designers to evaluate the physical security of the system. This work presents profiling-based cross-device power SCA attacks using deep learning techniques on…

The WaveDAQ is a newly-designed digitization Trigger and Data AcQuisition system (TDAQ) allowing Multi-gigasample waveform recording on a large amount of channels (up to 16384) by using the DRS4 analog switched capacitor array as…

In high energy physics experiments (HEP), high speed and fault resilient data communication is needed between detectors/sensors and the host PC. Transient faults can occur in the communication hardware due to various external effects like…

This paper presents a novel data detector ASIC for massive multiuser multiple-input multiple-output (MU-MIMO) wireless systems. The ASIC implements a modified version of the large-MIMO approximate message passing algorithm (LAMA), which…

With the new generation of the RPC, it is possible to work with induced signals of hundreds $\mu V$, hence the front-end electronics is an important and delicate part of the detector in order to get a detectable signal. The electronic chain…

A remote data acquisition chassis, called a HOTLink Rack Monitor, HRM, has been developed for use in the Fermilab control system. This chassis provides for 64 analog input channels, 8 analog output channels, and 8 bytes of digital I/O. The…

The Fermilab Accelerator Division, Instrumentation Department is adopting an open-source framework to replace our embedded VME-based data acquisition systems. Utilizing an iterative methodology, we first moved to embedded Linux, removing…

In this article, the performance of a fixed grid network is examined for various modulation formats to estimate the system's capacity and spectral efficiency. The optical In-phase Quadrature Modulator structure is used to build a fixed grid…

This paper presents two industry-grade datasets captured during an 8-hour continuous operation of the manufacturing assembly line at the Future Factories Lab, University of South Carolina, on 08/13/2024. The datasets adhere to industry…

To achieve the aim of the ITER Radial Neutron Camera Diagnostic, the data acquisition prototype must be compliant with a sustained 2 MHz peak event for each channel with 128 samples of 16 bits per event. The data is acquired and processed…

The multichannel data acquisition system is intended to be used in the EMMA experiment studying cosmic rays. The array will be in the Pihasalmi mine (central Finland) at a depth of about 85 m. The scintillator counters (SC-1) of the array…

Three generations of full-custom analog integrated circuits designed for low-power, high-speed sampling of Radio-Frequency (RF) transients in excess of the Nyquist minimum have been developed. These 0.25$\mu m$ CMOS devices are denoted the…

In this article it is presented an FPGA based $M$ulti-$V$oltage $T$hreshold (MVT) system which allows of sampling fast signals ($1-2$ ns rising and falling edge) in both voltage and time domain. It is possible to achieve a precision of time…

Analog to digital converters (ADCs) are a major contributor to the power consumption of multiple-input multiple-output (MIMO) receivers in large bandwidth millimeter-wave systems. Prior works have considered two mitigating solutions to…

We introduce an open-source architecture for next-generation Radio-Access Network baseband processing: 1024 latency-tolerant 32-bit RISC-V cores share 4 MiB of L1 memory via an ultra-low latency interconnect (7-11 cycles), a modular Direct…

Analog beamforming greatly reduces the implementation cost of massive antenna transceivers by using only one up/down-conversion chain. However, it incurs a large pilot overhead when used with conventional channel estimation (CE) techniques.…

Graphical Processing Units (GPUs) have recently become a valuable computing tool for the acquisition of data at high rates and for a relatively low cost. The devices work by parallelizing the code into thousands of threads, each executing a…