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This paper summarizes the idea of Subarray-Level Parallelism (SALP) in DRAM, which was published in ISCA 2012, and examines the work's significance and future potential. Modern DRAMs have multiple banks to serve multiple memory requests in…

Hardware Architecture · Computer Science 2018-05-08 Yoongu Kim , Vivek Seshadri , Donghyuk Lee , Jamie Liu , Onur Mutlu

We propose overcoming the memory capacity limitation of GPUs with high-capacity Storage-Class Memory (SCM) and DRAM cache. By significantly increasing the memory capacity with SCM, the GPU can capture a larger fraction of the memory…

Hardware Architecture · Computer Science 2024-03-15 Jeongmin Hong , Sungjun Cho , Geonwoo Park , Wonhyuk Yang , Young-Ho Gong , Gwangsun Kim

This paper investigates hardware-based memory compression designs to increase the memory bandwidth. When lines are compressible, the hardware can store multiple lines in a single memory location, and retrieve all these lines in a single…

Hardware Architecture · Computer Science 2018-07-23 Vinson Young , Sanjay Kariyappa , Moinuddin K. Qureshi

AI clusters today are one of the major uses of High Bandwidth Memory (HBM). However, HBM is suboptimal for AI workloads for several reasons. Analysis shows HBM is overprovisioned on write performance, but underprovisioned on density and…

To process data that do not fit in RAM, conventional wisdom would suggest using distributed approaches. However, recent research has demonstrated virtual memory's strong potential in scaling up graph mining algorithms on a single machine.…

Machine Learning · Computer Science 2016-04-12 Dezhi Fang , Duen Horng Chau

It has become increasingly difficult to understand the complex interaction between modern applications and main memory, composed of DRAM chips. Manufacturers are now selling and proposing many different types of DRAM, with each DRAM type…

Hardware Architecture · Computer Science 2019-10-21 Saugata Ghose , Tianshi Li , Nastaran Hajinazar , Damla Senol Cali , Onur Mutlu

Limited memory bandwidth is a critical bottleneck in modern systems. 3D-stacked DRAM enables higher bandwidth by leveraging wider Through-Silicon-Via (TSV) channels, but today's systems cannot fully exploit them due to the limited internal…

Hardware Architecture · Computer Science 2015-06-11 Donghyuk Lee , Gennady Pekhimenko , Samira Khan , Saugata Ghose , Onur Mutlu

Intel Optane DC Persistent Memory (Optane PMM) is a new kind of byte-addressable memory with higher density and lower cost than DRAM. This enables the design of affordable systems that support up to 6TB of randomly accessible memory. In…

Distributed, Parallel, and Cluster Computing · Computer Science 2020-02-25 Gurbinder Gill , Roshan Dathathri , Loc Hoang , Ramesh Peri , Keshav Pingali

Analog processing-using-memory (PUM; a.k.a. in-memory computing) makes use of electrical interactions inside memory arrays to perform bulk matrix-vector multiplication (MVM) operations. However, many popular matrix-based kernels need to…

Hardware Architecture · Computer Science 2026-05-06 Ryan Wong , Ben Feinberg , Saugata Ghose

DRAM-based main memory is used in nearly all computing systems as a major component. One way of overcoming the main memory bottleneck is to move computation near memory, a paradigm known as processing-in-memory (PiM). Recent PiM techniques…

Hardware Architecture · Computer Science 2022-06-02 Ataberk Olgun , Juan Gomez Luna , Konstantinos Kanellopoulos , Behzad Salami , Hasan Hassan , Oguz Ergin , Onur Mutlu

Efficient and coherent data retrieval and storage are essential for harnessing quantum algorithms' speedup. Such a fundamental task is addressed by a quantum Random Access Memory (qRAM). Despite their promising scaling properties, current…

Quantum Physics · Physics 2026-04-09 Giuseppe De Riso , Giuseppe Catalano , Seth Lloyd , Vittorio Giovannetti , Dario De Santis

The design of the buffer manager in database management systems (DBMSs) is influenced by the performance characteristics of volatile memory (DRAM) and non-volatile storage (e.g., SSD). The key design assumptions have been that the data must…

Databases · Computer Science 2019-01-31 Joy Arulraj , Andy Pavlo , Krishna Teja Malladi

Even with generational improvements in DRAM technology, memory access latency still remains the major bottleneck for application accelerators, primarily due to limitations in memory interface IPs which cannot fully account for variations in…

Hardware Architecture · Computer Science 2021-08-24 Sasindu Wijeratne , Sanket Pattnaik , Zhiyu Chen , Rajgopal Kannan , Viktor Prasanna

As machine learning spreads into more and more application areas, micro controllers and low power CPUs are increasingly being used to perform inference with machine learning models. The capability to deploy onto these limited hardware…

Distributed, Parallel, and Cluster Computing · Computer Science 2020-11-18 Peter Blacker , Christopher Paul Bridges , Simon Hadfield

In recent years, there is an increasing demand of big memory systems so to perform large scale data analytics. Since DRAM memories are expensive, some researchers are suggesting to use other memory systems such as non-volatile memory (NVM)…

Performance · Computer Science 2016-10-03 Gaoying Ju , Yongkun Li , Yinlong Xu , Jiqiang Chen , John C. S. Lui

Emerging non-volatile main memory (NVRAM) technologies provide byte-addressability, low idle power, and improved memory-density, and are likely to be a key component in the future memory hierarchy. However, a critical challenge in achieving…

Data Structures and Algorithms · Computer Science 2019-08-22 Guy E. Blleloch , Yan Gu

Existing memory management mechanisms used in commodity computing machines typically adopt hardware based address interleaving and OS directed random memory allocation to service generic application requests. These conventional memory…

Operating Systems · Computer Science 2017-04-06 Lei Liu

Large-scale genomic workflows used in precision medicine can process datasets spanning tens to hundreds of gigabytes per sample, leading to high memory spikes, intensive disk I/O, and task failures due to out-of-memory errors. Simple static…

Distributed, Parallel, and Cluster Computing · Computer Science 2025-11-21 Daniel Mas Montserrat , Ray Verma , Míriam Barrabés , Francisco M. de la Vega , Carlos D. Bustamante , Alexander G. Ioannidis

The latest trends in high-performance computing systems show an increasing demand on the use of a large scale multicore systems in a efficient way, so that high compute-intensive applications can be executed reasonably well. However, the…

Distributed, Parallel, and Cluster Computing · Computer Science 2013-02-25 Juliana M. N. Silva , Cristina Boeres , Lúcia M. A. Drummond , Artur A. Pessoa

This paper summarizes our work on experimental characterization and analysis of reduced-voltage operation in modern DRAM chips, which was published in SIGMETRICS 2017, and examines the work's significance and future potential. We take a…