Related papers: Fundamental Results for a Generic Implementation o…
In these series of multi-part papers, a systematic study of fundamental limits of communications in interference networks is established. Here, interference network is referred to as a general single-hop communication scenario with…
A tight lower bound for required I/O when computing an ordinary matrix-matrix multiplication on a processor with two layers of memory is established. Prior work obtained weaker lower bounds by reasoning about the number of segments needed…
We study the inherent space requirements of shared storage algorithms in asynchronous fault-prone systems. Previous works use codes to achieve a better storage cost than the well-known replication approach. However, a closer look reveals…
Memory latency, bandwidth, capacity, and energy increasingly limit performance. In this paper, we reconsider proposed system architectures that consist of huge (many-terabyte to petabyte scale) memories shared among large numbers of CPUs.…
One of the main problems for the future of practical quantum computing is to stabilize the computation against unwanted interactions with the environment and imperfections in the applied operations. Existing proposals for quantum memories…
Memory-augmented neural networks consisting of a neural controller and an external memory have shown potentials in long-term sequential learning. Current RAM-like memory models maintain memory accessing every timesteps, thus they do not…
We consider a fundamental problem concerning the deployment of a wireless robotic network: to fulfill various end-to-end performance requirements, a "sufficient" number of robotic relays must be deployed to ensure that links are of…
In the earlier version of this paper, it was wrongly claimed that time-sharing is required to achieve the capacity region of the Gaussian interference channel to within one bit, especially at corner points. The flaw in the argument of the…
The Interference Channels (ICs) represent fundamental building blocks of wireless communication networks. Despite considerable progress in network information theory, available capacity results for ICs, specifically those with more than two…
The future of main memory appears to lie in the direction of new technologies that provide strong capacity-to-performance ratios, but have write operations that are much more expensive than reads in terms of latency, bandwidth, and energy.…
Quantum and private communications are affected by a fundamental limitation which severely restricts the optimal rates that are achievable by two distant parties. To overcome this problem, one needs to introduce quantum repeaters and, more…
We study the computational cost of differential privacy in terms of memory efficiency. While the trade-off between accuracy and differential privacy is well-understood, the inherent cost of privacy regarding memory use remains largely…
Control barrier functions are widely used to enforce safety properties in robot motion planning and control. However, the problem of constructing barrier functions online and synthesizing safe controllers that can deal with the associated…
Quantum memory is important to quantum information processing in many ways: a synchronization device to match various processes within a quantum computer, an identity quantum gate that leaves any state unchanged, and a tool to convert…
Interference is usually viewed as an obstacle to communication in wireless networks. This paper proposes a new strategy, compute-and-forward, that exploits interference to obtain significantly higher rates between users in a network. The…
High reliability and availability of communication services is a key requirement that needs to be ensured by service providers. Since the direct line-of-sight (LOS) beam is prone to blockage in indoor optical wireless communication systems,…
We give lower bounds on the communication complexity required to solve several computational problems in a distributed-memory parallel machine, namely standard matrix multiplication, stencil computations, comparison sorting, and the Fast…
Many machine learning approaches are characterized by information constraints on how they interact with the training data. These include memory and sequential access constraints (e.g. fast first-order methods to solve stochastic…
Ubiquitous multicore processors nowadays rely on an integrated packet-switched network for cores to exchange and share data. The performance of these intra-chip networks is a key determinant of the processor speed and, at high core counts,…
The advancement of manufacturing technologies has enabled the integration of more intellectual property (IP) cores on the same system-on-chip (SoC). Scalable and high throughput on-chip communication architecture has become a vital…