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Fusion simulations have traditionally required the use of leadership scale High Performance Computing (HPC) resources in order to produce advances in physics. The impressive improvements in compute and memory capacity of many-GPU compute…

Distributed, Parallel, and Cluster Computing · Computer Science 2022-07-12 Emily A. Belli , Jeff Candy , Igor Sfiligoi , Frank Würthwein

Multicore CPU architectures have been established as a structure for general-purpose systems for high-performance processing of applications. Recent multicore CPU has evolved as a system architecture based on non-uniform memory…

Distributed, Parallel, and Cluster Computing · Computer Science 2021-01-26 Geunsik Lim , Sang-Bum Suh

This paper presents a massively parallel and scalable neuromorphic cortex simulator designed for simulating large and structurally connected spiking neural networks, such as complex models of various areas of the cortex. The main novelty of…

Neural and Evolutionary Computing · Computer Science 2018-03-09 Runchun Wang , Chetan Singh Thakur , Andre van Schaik

The rapidly growing popularity and scale of data-parallel workloads demand a corresponding increase in raw computational power of GPUs (Graphics Processing Units). As single-GPU systems struggle to satisfy the performance demands, multi-GPU…

Distributed, Parallel, and Cluster Computing · Computer Science 2018-11-15 Yifan Sun , Trinayan Baruah , Saiful A. Mojumder , Shi Dong , Rafael Ubal , Xiang Gong , Shane Treadway , Yuhui Bao , Vincent Zhao , José L. Abellán , John Kim , Ajay Joshi , David Kaeli

The sizes of GPU applications are rapidly growing. They are exhausting the compute and memory resources of a single GPU, and are demanding the move to multiple GPUs. However, the performance of these applications scales sub-linearly with…

Hardware Architecture · Computer Science 2020-08-11 Saiful A. Mojumder , Yifan Sun , Leila Delshadtehrani , Yenai Ma , Trinayan Baruah , José L. Abellán , John Kim , David Kaeli , Ajay Joshi

Running neural networks (NNs) on microcontroller units (MCUs) is becoming increasingly important, but is very difficult due to the tiny SRAM size of MCU. Prior work proposes many algorithm-level techniques to reduce NN memory footprints,…

Hardware Architecture · Computer Science 2021-09-02 Hongyu Miao , Felix Xiaozhu Lin

The emergence of Big Data in recent years has resulted in a growing need for efficient data processing solutions. While infrastructures with sufficient compute power are available, the I/O bottleneck remains. The Linux page cache is an…

Distributed, Parallel, and Cluster Computing · Computer Science 2021-01-06 Hoang-Dung Do , Valerie Hayot-Sasson , Rafael Ferreira da Silva , Christopher Steele , Henri Casanova , Tristan Glatard

Processing large-scale graph datasets is computationally intensive and time-consuming. Processor-centric CPU and GPU architectures, commonly used for graph applications, often face bottlenecks caused by extensive data movement between the…

Distributed, Parallel, and Cluster Computing · Computer Science 2026-02-11 Marzieh Barkhordar , Alireza Tabatabaeian , Mohammad Sadrosadati , Christina Giannoula , Juan Gomez Luna , Izzat El Hajj , Onur Mutlu , Alaa R. Alameldeen

The increasing number of threads inside the cores of a multicore processor, and competitive access to the shared cache memory, become the main reasons for an increased number of competitive cache misses and performance decline. Inevitably,…

Hardware Architecture · Computer Science 2017-01-09 Milcho Prisagjanec , Pece Mitrevski

Growing power dissipation due to high performance requirement of processor suggests multicore processor technology, which has become the technology for present and next decade. Research advocates asymmetric multi-core processor system for…

Distributed, Parallel, and Cluster Computing · Computer Science 2017-02-15 Alan David

This short report describes the scaling, up to 1024 software processes and hardware cores, of a distributed simulator of plastic spiking neural networks. A previous report demonstrated good scalability of the simulator up to 128 processes.…

The design space exploration of scaled-out manycores for communication-intensive applications (e.g., graph analytics and sparse linear algebra) is hampered due to either lack of scalability or accuracy of existing frameworks at simulating…

Hardware Architecture · Computer Science 2024-04-23 Marcelo Orenes-Vera , Esin Tureci , Margaret Martonosi , David Wentzlaff

Parallel programming is emerging fast and intensive applications need more resources, so there is a huge demand for on-chip multiprocessors. Accessing L1 caches beside the cores are the fastest after registers but the size of private caches…

Performance · Computer Science 2016-09-27 Diman Zad Tootaghaj , Farshid Farhat

The impact of transformer networks is booming, yet, they come with significant computational complexity. It is therefore essential to understand how to optimally map and execute these networks on modern neural processor hardware. So far,…

Hardware Architecture · Computer Science 2024-06-17 Steven Colleman , Arne Symons , Victor J. B. Jung , Marian Verhelst

The NEURON simulator has been developed over the past three decades and is widely used by neuroscientists to model the electrical activity of neuronal networks. Large network simulation projects using NEURON have supercomputer allocations…

Neurons and Cognition · Quantitative Biology 2019-01-31 Pramod Kumbhar , Michael Hines , Jeremy Fouriaux , Aleksandr Ovcharenko , James King , Fabien Delalondre , Felix Schürmann

Graphics Processing Units (GPUs) are becoming popular accelerators in modern High-Performance Computing (HPC) clusters. Installing GPUs on each node of the cluster is not efficient resulting in high costs and power consumption as well as…

Distributed, Parallel, and Cluster Computing · Computer Science 2016-06-15 Javier Prades , Blesson Varghese , Carlos Reano , Federico Silla

Real-time simulation of a large-scale biologically representative spiking neural network is presented, through the use of a heterogeneous parallelisation scheme and SpiNNaker neuromorphic hardware. A published cortical microcircuit model is…

Emerging Technologies · Computer Science 2021-04-28 Oliver Rhodes , Luca Peres , Andrew G. D. Rowley , Andrew Gait , Luis A. Plana , Christian Brenninkmeijer , Steve B. Furber

Modern computing platforms tend to deploy multiple GPUs (2, 4, or more) on a single node to boost system performance, with each GPU having a large capacity of global memory and streaming multiprocessors (SMs). GPUs are an expensive…

Distributed, Parallel, and Cluster Computing · Computer Science 2021-07-20 Chao Chen , Chris Porter , Santosh Pande

Major chip manufacturers have all introduced multicore microprocessors. Multi-socket systems built from these processors are used for running various server applications. Depending on the application that is run on the system, remote memory…

Distributed, Parallel, and Cluster Computing · Computer Science 2019-08-13 Murthy Durbhakula

This paper presents the Neural Cache architecture, which re-purposes cache structures to transform them into massively parallel compute units capable of running inferences for Deep Neural Networks. Techniques to do in-situ arithmetic in…

Hardware Architecture · Computer Science 2018-05-11 Charles Eckert , Xiaowei Wang , Jingcheng Wang , Arun Subramaniyan , Ravi Iyer , Dennis Sylvester , David Blaauw , Reetuparna Das