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Integer Linear Programming (ILP) is widely used for solving real-world optimization problems, including network routing, map routing, and traffic scheduling. However, ILP algorithms are sparse and branch-intensive, making them inefficient…

Hardware Architecture · Computer Science 2026-05-28 Siddhartha Raman Sundara Raman , Lizy K John , Jaydeep P. Kulkarni

Computing has a huge memory problem. The memory system, consisting of multiple technologies at different levels, is responsible for most of the energy consumption, performance bottlenecks, robustness problems, monetary cost, and hardware…

Hardware Architecture · Computer Science 2025-09-05 Onur Mutlu , Ataberk Olgun , Ismail Emir Yuksel

This report describes 1) how we use Intel's Optane DCPMM in the memory Mode. We investigate the the scalability of applications on a single Optane machine, using Subgraph counting as memory-intensive graph problem. We test with various…

Distributed, Parallel, and Cluster Computing · Computer Science 2021-09-24 Ahmet Uyar , Selahattin Akkas , Jiayu Li , Judy Fox

Efficient on-device neural network (NN) inference offers predictable latency, improved privacy and reliability, and lower operating costs for vendors than cloud-based inference. This has sparked recent development of microcontroller-scale…

Machine Learning · Computer Science 2025-11-03 Josh Millar , Yushan Huang , Sarab Sethi , Hamed Haddadi , Anil Madhavapeddy

Although a data processing system often works as a batch processing system, many enterprises deploy such a system as a service, which we call the service-oriented data processing system. It has been shown that in-memory data processing…

Distributed, Parallel, and Cluster Computing · Computer Science 2017-03-30 Xuanhua Shi , Xiong Zhang , Ligang He , Hai Jin , Zhixiang Ke , Song Wu

Compute in-memory (CIM) is a promising technique that minimizes data transport, the primary performance bottleneck and energy cost of most data intensive applications. This has found wide-spread adoption in accelerating neural networks for…

Hardware Architecture · Computer Science 2020-08-18 Brian Crafton , Samuel Spetalnick , Gauthaman Murali , Tushar Krishna , Sung-Kyu Lim , Arijit Raychowdhury

Caches at CPU nodes in disaggregated memory architectures amortize the high data access latency over the network. However, such caches are fundamentally unable to improve performance for workloads requiring pointer traversals across linked…

Distributed, Parallel, and Cluster Computing · Computer Science 2024-12-17 Yupeng Tang , Seung-seob Lee , Abhishek Bhattacharjee , Anurag Khandelwal

Compute-in-SRAM architectures offer a promising approach to achieving higher performance and energy efficiency across a range of data-intensive applications. However, prior evaluations have largely relied on simulators or small prototypes,…

Hardware Architecture · Computer Science 2025-09-09 Niansong Zhang , Wenbo Zhu , Courtney Golden , Dan Ilan , Hongzheng Chen , Christopher Batten , Zhiru Zhang

As data volumes grow across applications, analytics of large amounts of data is becoming increasingly important. Big data processing frameworks such as Apache Hadoop, Apache AsterixDB, and Apache Spark have been built to meet this demand. A…

Distributed, Parallel, and Cluster Computing · Computer Science 2022-12-15 Avinash Kumar

Multi-threaded applications are capable of exploiting the full potential of many-core systems. However, Network-on-Chip (NoC) based inter-core communication in many-core systems is responsible for 60-75% of the miss latency experienced by…

Hardware Architecture · Computer Science 2021-01-05 Abhijit Das , John Jose , Prabhat Mishra

We are living in the era of Big Data and witnessing the explosion of data. Given that the limitation of CPU and I/O in a single computer, the mainstream approach to scalability is to distribute computations among a large number of…

Distributed, Parallel, and Cluster Computing · Computer Science 2021-07-27 Bingbing Rao , Liqiang Wang

The rise of disaggregated AI GPUs has exposed a critical bottleneck in large-scale attention workloads: non-uniform memory access (NUMA). As multi-chiplet designs become the norm for scaling compute capabilities, memory latency and…

Hardware Architecture · Computer Science 2025-11-05 Mansi Choudhary , Karthik Sangaiah , Sonali Singh , Muhammad Osama , Lisa Wu Wills , Ganesh Dasika

Much like on-premises systems, the natural choice for running database analytics workloads in the cloud is to provision a cluster of nodes to run a database instance. However, analytics workloads are often bursty or low volume, leaving…

Databases · Computer Science 2019-11-27 Matthew Perron , Raul Castro Fernandez , David DeWitt , Samuel Madden

Hadoop is emerging as the primary data hub in enterprises, and SQL represents the de facto language for data analysis. This combination has led to the development of a variety of SQL-on-Hadoop systems in use today. While the various…

Databases · Computer Science 2018-04-03 Ashish Tapdiya , Daniel Fabbri

High Performance and Energy Efficiency are critical requirements for Internet of Things (IoT) end-nodes. Exploiting tightly-coupled clusters of programmable processors (CMPs) has recently emerged as a suitable solution to address this…

Hardware Architecture · Computer Science 2023-09-06 Jie Chen , Igor Loi , Eric Flamand , Giuseppe Tagliavini , Luca Benini , Davide Rossi

As exascale systems reach unprecedented concurrency, traditional performance analysis tools struggle with the overhead of massive-scale telemetry. We present an accelerated infrastructure for the hpcanalysis framework that leverages a…

Distributed, Parallel, and Cluster Computing · Computer Science 2026-05-12 Dragana Grbic

Complex applications running on multicore processors show a rich performance phenomenology. The growing number of cores per ccNUMA domain complicates performance analysis of memory-bound code since system noise, load imbalance, or…

Distributed, Parallel, and Cluster Computing · Computer Science 2020-11-03 Ayesha Afzal , Georg Hager , Gerhard Wellein

In cloud ML inference systems, batching is an essential technique to increase throughput which helps optimize total-cost-of-ownership. Prior graph batching combines the individual DNN graphs into a single one, allowing multiple inputs to be…

Distributed, Parallel, and Cluster Computing · Computer Science 2020-10-27 Yujeong Choi , Yunseong Kim , Minsoo Rhu

Multicore systems present on-board memory hierarchies and communication networks that influence performance when executing shared memory parallel codes. Characterising this influence is complex, and understanding the effect of particular…

Distributed, Parallel, and Cluster Computing · Computer Science 2018-10-01 O. G. Lorenzo , M. L. Becoña , T. F. Pena , J. C. Cabaleiro , J. A. Lorenzo , F. F. Rivera

Poor DRAM technology scaling over the course of many years has caused DRAM-based main memory to increasingly become a larger system bottleneck. A major reason for the bottleneck is that data stored within DRAM must be moved across a…

Hardware Architecture · Computer Science 2018-02-02 Saugata Ghose , Kevin Hsieh , Amirali Boroumand , Rachata Ausavarungnirun , Onur Mutlu
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