Related papers: FPGA based High Speed Data Acquisition System for …

Traditionally, high energy physics (HEP) experiments have relied on x86 CPUs for the majority of their significant computing needs. As the field looks ahead to the next generation of experiments such as DUNE and the High-Luminosity LHC, the…

This work concerns physical layer collision recovery for cheap sensors with allowed variations in frequency and delay of their communications. The work is presented as a generic, communication theoretic framework and demonstrated using UHF…

The POEMMA-Balloon with Radio (PBR) mission incorporates an advanced data processing system (DP) to enable the detection and characterization of ultra-high-energy cosmic rays and astrophysical neutrinos. The data acquisition (DAQ) system…

We present a novel application of the machine learning / artificial intelligence method called boosted decision trees to estimate physical quantities on field programmable gate arrays (FPGA). The software package fwXmachina features a new…

The data acquisition system (DAQ) of the future Cherenkov Telescope Array (CTA) must be ef- ficient, modular and robust to be able to cope with the very large data rate of up to 550 Gbps coming from many telescopes with different…

The XENON1T liquid xenon time projection chamber is the most sensitive detector built to date for the measurement of direct interactions of weakly interacting massive particles with normal matter. The data acquisition system (DAQ) is…

The Global Event Processor (GEP) FPGA is an area-constrained, performance-critical element of the Large Hadron Collider's (LHC) ATLAS experiment. It needs to very quickly determine which small fraction of detected events should be retained…

Power consumption will be a key constraint on the future growth of Distributed High Throughput Computing (DHTC) as used by High Energy Physics (HEP). This makes performance-per-watt a crucial metric for selecting cost-efficient computing…

We present a data acquisition~(DAQ) software based on the MIDAS framework, specifically for gaseous detectors to support the detector deployments and applications. It implements a comprehensive suite of functions, including parameter…

We are developing a new readout board with a newer generation field-programmable gate array (FPGA) and the 10-gigabit ethernet to improve the performance and usability of the current readout board based on the 1-gigabit Ethernet. In this…

Accelerating Human Action Recognition (HAR) efficiently for real-time surveillance and robotic systems on edge chips remains a challenging research field, given its high computational and memory requirements. This paper proposed an…

The use of reconfigurable computing, and FPGAs in particular, to accelerate computational kernels has the potential to be of great benefit to scientific codes and the HPC community in general. However, whilst recent advanced in FPGA tooling…

Reconfigurable architectures like Field Programmable Gate Arrays (FPGAs) have been used for accelerating computations in several domains because of their unique combination of flexibility, performance, and power efficiency. However, FPGAs…

One of the optimization goals of a particle accelerator is to reach the highest possible beam peak current. For that to happen the electron bunch propagating through the accelerator should be kept relatively short along the direction of its…

A fast data acquisition (DAQ) system for axion dark matter searches utilizing a microwave resonant cavity, also known as axion haloscope searches, has been developed with a two-channel digitizer that can sample 16-bit amplitudes at rates up…

Hardware acceleration has emerged as a key research topic for supporting computationally intensive signal processing and artificial intelligence applications in 6G research and development studies. This paper presents an RF Network on Chip…

Field-Programmable Gate Arrays (FPGAs) have provided Thomas Jefferson National Accelerator Facility (Jefferson Lab) with versatile VME-based data acquisition and control interfaces with minimal development times. FPGA designs have been used…

This paper presents an RDMA over Ethernet protocol used for data acquisition systems, currently under development at the ESRF. The protocol is implemented on Xilinx Ultrascale + FPGAs thanks to the 100G hard MAC IP. The proposed protocol is…

The upcoming PandaX-xT experiment will deploy over 3,000 readout channels operating at a 500 MSa/s sampling rate, generating a sustained data bandwidth up to 1.6 GB/s. To meet this demanding requirement, we present AURORA, a…

We implemented a real-time data processor (rta-dp) framework that can be used to develop real-time analysis pipelines and data handling systems to manage high-throughput data streams with distributed applications in the context of ground…