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In this paper, we present a novel cache design based on Multi-Level Cell Spin-Transfer Torque RAM (MLC STTRAM) that can dynamically adapt the set capacity and associativity to use efficiently the full potential of MLC STTRAM. We exploit the…

Hardware Architecture · Computer Science 2017-06-13 Amin Jadidi , Mohammad Arjomand , Mahmut T. Kandemir , Chita R. Das

NAND flash-based Solid State Drives (SSDs), which are widely used from embedded systems to enterprise servers, are enhancing performance by exploiting the parallelism of NAND flash memories. To cope with the performance improvement of SSDs,…

Hardware Architecture · Computer Science 2017-04-12 Yeong-Jae Woo , Sang Lyul Min

Recently, 3D SSDs are widely adopted in PCs, data centers, and cloud storage systems. To increase capacity, high bit-density cells, such as Triple-Level Cell (TLC), are utilized within 3D SSDs. However, due to the inferior performance of…

Hardware Architecture · Computer Science 2024-10-15 Xufeng Yang , Zhengjian Cong , Congming Gao

With emerging storage-class memory (SCM) nearing commercialization, there is evidence that it will deliver the much-anticipated high density and access latencies within only a few factors of DRAM. Nevertheless, the latency-sensitive nature…

The performance and capacity of solid-state drives (SSDs) are continuously improving to meet the increasing demands of modern data-intensive applications. Unfortunately, communication between the SSD controller and memory chips (e.g., 2D/3D…

In cost-sensitive deployments, RAID arrays may combine SSDs with different performance levels. Such heterogeneity arises when aging SSDs degrade yet remain usable, or when failed drives are replaced with new devices of explicitly better…

Operating Systems · Computer Science 2026-04-03 Jialin Liu , Liang Shi , Dingcui Yu

As the amount of data produced in society continues to grow at an exponential rate, modern applications are incurring significant performance and energy penalties due to high data movement between the CPU and memory/storage. While…

Hardware Architecture · Computer Science 2024-03-12 Ryan Wong , Nikita Kim , Kevin Higgs , Sapan Agarwal , Engin Ipek , Saugata Ghose , Ben Feinberg

This paper summarizes our work on experimentally characterizing, mitigating, and recovering read disturb errors in multi-level cell (MLC) NAND flash memory, which was published in DSN 2015, and examines the work's significance and future…

Hardware Architecture · Computer Science 2018-05-10 Yu Cai , Yixin Luo , Saugata Ghose , Erich F. Haratsch , Ken Mai , Onur Mutlu

In this work, we propose a novel coding scheme which based on the characteristics of NAND flash cells, generates codewords that reduce the energy consumption and improve the reliability of solid-state drives. This novel coding scheme,…

Information Theory · Computer Science 2019-07-08 Armin Ahmadzadeh , Omid Hajihassani , Pooria Taheri , Seyed Hossein Khasteh

Solid-state storage architectures based on NAND or emerging memory devices (SSD), are fundamentally architected and optimized for both reliability and performance. Achieving these simultaneous goals requires co-design of memory components…

Hardware Architecture · Computer Science 2026-03-20 Jay Sarkar , Vamsi Pavan Rayaprolu , Abhijeet Bhalerao

Resource utilization is one of the emerging problems in many-chip SSDs. In this paper, we propose Sprinkler, a novel device-level SSD controller, which targets maximizing resource utilization and achieving high performance without…

Hardware Architecture · Computer Science 2017-05-15 Myoungsoo Jung , Mahmut T. Kandemir

Modern external memory is represented by several device classes. At present, HDD, SATA SSD and NVMe SSD are widely used. Recently ultra-low latency SSD such as Intel Optane became available on the market. Each of these types exhibits it's…

Distributed, Parallel, and Cluster Computing · Computer Science 2021-02-23 Ruslan Savchenko

With the ever-increasing amount of data generate in the world, estimated to reach over 200 Zettabytes by 2025, pressure on efficient data storage systems is intensifying. The shift from HDD to flash-based SSD provides one of the most…

Operating Systems · Computer Science 2023-07-25 Nick Tehrany , Krijn Doekemeijer , Animesh Trivedi

In modern solid-state drives (SSDs), the indexing of flash pages is a critical component in their storage controllers. It not only affects the data access performance, but also determines the efficiency of the precious in-device DRAM…

Operating Systems · Computer Science 2023-01-03 Jinghan Sun , Shaobo Li , Yunxin Sun , Chao Sun , Dejan Vucinic , Jian Huang

The rapid expansion of mass spectrometry (MS) data, now exceeding hundreds of terabytes, poses significant challenges for efficient, large-scale library search - a critical component for drug discovery. Traditional processors struggle to…

Modern dense Flash memory devices operate at very low error rates, which require powerful error correcting coding (ECC) techniques. An emerging class of graph-based ECC techniques that has broad applications is the class of…

Information Theory · Computer Science 2019-09-25 Ahmed Hareedy , Homa Esfahanizadeh , Lara Dolecek

Superconducting Digital (SCD) technology offers significant potential for enhancing the performance of next generation large scale compute workloads. By leveraging advanced lithography and a 300 mm platform, SCD devices can reduce energy…

Recommendation system has gained a large popularity for a variety of personalized suggestion tasks, but the ever-increasing number of user data makes real-time processing of recommendation systems difficult. NAND flash memory-based…

Hardware Architecture · Computer Science 2026-04-29 Jangho Baik , Sunghyun Kim , Gisan Ji , Wonbo Shim , Sungju Ryu

Software-defined networking (SDN) and software-defined flash (SDF) have been serving as the backbone of modern data centers. They are managed separately to handle I/O requests. At first glance, this is a reasonable design by following the…

Operating Systems · Computer Science 2023-09-14 Benjamin Reidys , Yuqi Xue , Daixuan Li , Bharat Sukhwani , Wen-mei Hwu , Deming Chen , Sameh Asaad , Jian Huang

In this paper, we propose a 'full-stack' solution to designing high capacity and low latency on-chip cache hierarchies by starting at the circuit level of the hardware design stack. First, we propose a novel Gain Cell (GC) design using…

Hardware Architecture · Computer Science 2021-10-07 Sarabjeet Singh , Neelam Surana , Pranjali Jain , Joycee Mekie , Manu Awasthi