Related papers: Compact Model of Nanowire Tunneling FETs Including…
Phonon-assisted tunneling rates are evaluated for a well isolated double dot system defined in a GaAs semiconductor heterostructure of finite thickness. A separable model for the confining potential allows accurate determinations of doublet…
We present a compact model for Tunnel Field Effect Transistors (TFET), that captures sev- eral non-idealities such as the Trap Assisted Tunneling (TAT) originating from interface traps (Dit), along with Verilog-A implementation. We show…
We report the capability to simulate in a quantum mechanical tight-binding (TB) atomistic fashion NW devices featuring several hundred to millions of atoms and diameter up to 18 nm. Such simulations go far beyond what is typically…
Current-voltage characteristics of suspended single-wall carbon nanotube quantum dots show a series of steps equally spaced in voltage. The energy scale of this harmonic, low-energy excitation spectrum is consistent with that of the…
The current work explores a geometrically engineered dual gate GaAs nanowire FET with state of the art miniaturized dimensions for high performance charge qubit operation at room temperature. Relevant gate voltages in such device can create…
As a result of suppressed phonon conduction, large improvements of the thermoelectric figure of merit, ZT, have been recently reported for nanostructures compared to the raw materials' ZT values. It has also been suggested that low…
An important consideration in miniaturizing transistors is maximizing the coupling between the gate and the semiconductor channel. A nanowire with a coaxial metal gate provides optimal gate-channel coupling, but has only been realized for…
As metal-oxide-semiconductor field-effect transistors (MOSFET) channel lengths (Lg) are scaled to lengths shorter than Lg<8 nm source-drain tunneling starts to become a major performance limiting factor. In this scenario a heavier transport…
Many electrical applications of quantum dots rely on capacitively coupled gates; therefore, to make reliable devices we need those gate capacitances to be predictable and reproducible. We demonstrate in silicon nanowire quantum dots that…
A simulation methodology for ultra-scaled InAs quantum well field effect transistors (QWFETs) is presented and used to provide design guidelines and a path to improve device performance. A multiscale modeling approach is adopted, where…
Recently, short channel effects (SCE) and power consumption dissipation problems pose big challenges which need imperative actions to be taken to deal with for field effect transistor to further scale down as semiconductor technology enters…
Earlier, in the CINT program at Los Alamos National Laboratory, we focused ultrafast mode-locked lasers on the tip-sample junction of a scanning tunneling microscope to generate currents at hundreds of harmonics of the laser pulse…
In this work, we simulate the expected device performance and the scaling perspectives of Carbon nanotube Field Effect Transistors (CNT-FETs), with doped source and drain extensions. The simulations are based on the self-consistent solution…
This work presents a novel general compact model for 7nm technology node devices like FinFETs. As an extension of previous conventional compact model that based on some less accurate elements including one-dimensional Poisson equation for…
In this paper we propose a modified structure of TFET incorporating ferroelectric oxide as the complementary gate dielectric operating in negative capacitance zone, called the Negative Capacitance Tunnel FET (NCTFET). The proposed device…
In this paper, we develop an explicit model to predict the DC electrical behavior in ultra-thin surrounding gate junctionless nanowire FET. The proposed model takes into account 2D electrical and geometrical confinements of carrier charge…
Low dimensional materials provide the possibility of improved thermoelectric performance due to the additional length scale degree of freedom for engineering their electronic and thermal properties. As a result of suppressed phonon…
A simulation framework that couples atomistic electronic structures to Boltzmann transport formalism is developed and applied to calculate the transport characteristics of thin silicon nanowires (NWs) up to 12nm in diameter. The…
We presents a data-calibrated compact model of carbon nanotube (CNT) field-effect transistors (CNFETs) based on the virtual-source (VS) approach, describing the intrinsic current-voltage and charge-voltage characteristics. The features of…
Vertical tunneling field-effect-transistor (FET) based on graphene heterojunctions with layers of hBN is simulated by self-consistent quantum transport simulations. It is found that the asymmetric p-type and n-type conduction is due to work…