Related papers: Fast Prefix Adders for Non-Uniform Input Arrival T…
Robustness is as important as efficiency in air transportation. All components in the air traffic system are connected to form an interactive network. So, a disturbance that occurs in one component, for example, a severe delay at an…
In this paper, we report an optimized union-find (UF) algorithm that can label the connected components on a 2D image efficiently by employing the GPU architecture. The proposed method contains three phases: UF-based local merge, boundary…
There are two intertwined factors that affect performance of concurrent data structures: the ability of processes to access the data in parallel and the cost of synchronization. It has been observed that for a large class of…
Parallel computation enables multiple processors to execute different parts of a task simultaneously, improving processing speed and efficiency. In quantum computing, parallel gate implementation involves executing gates independently in…
Friedrichs et al. (TC 2018) showed that metastability can be contained when sorting inputs arising from time-to-digital converters, i.e., measurement values can be correctly sorted without resolving metastability using synchronizers first.…
Recent works proposed the relaying at the MAC layer in cognitive radio networks whereby the primary packets are forwarded by the secondary node maintaining an extra queue devoted to the relaying function. However, relaying of primary…
A quantum computer consists of a set of quantum bits upon which operations called gates are applied to perform computations. In order to perform quantum algorithms, physicists would like to design arbitrary gates to apply to quantum bits.…
We use exponential start time clustering to design faster and more work-efficient parallel graph algorithms involving distances. Previous algorithms usually rely on graph decomposition routines with strict restrictions on the diameters of…
This paper presents an approximate signed multiplier architecture that incorporates a sign-focused compressor, specifically designed for edge detection applications in machine learning and signal processing. The multiplier incorporates two…
The back-pressure algorithm is a well-known throughput-optimal algorithm. However, its delay performance may be quite poor even when the traffic load is not close to network capacity due to the following two reasons. First, each node has to…
Combinational or Classical logic circuits dissipate heat for every bit of information that is lost. Information is lost when the input vector cannot be recovered from its corresponding output vector. Reversible logic circuit implements only…
In the Partially Embedded Planarity problem, we are given a graph $G$ together with a topological drawing of a subgraph $H$ of $G$. The task is to decide whether the drawing can be extended to a drawing of the whole graph such that no two…
Inter-domain Traffic Engineering for multi-homed networks faces a scalability challenge, as the size of BGP routing table continue to grow. In this context, the choice of the best path must be made potentially for each destination prefix,…
We present a new adaptive parallel algorithm for the challenging problem of multi-dimensional numerical integration on massively parallel architectures. Adaptive algorithms have demonstrated the best performance, but efficient many-core…
Generators of arithmetic circuits can automatically deliver various implementations of arithmetic circuits that show different tradeoffs between the key circuit parameters (delay, area, power consumption). However, existing…
We demonstrate the applicability of a universal gate set in the parity encoding, which is a dual to the standard gate model, by exploring several quantum gate algorithms such as the quantum Fourier transform and quantum addition. Embedding…
Reducing delay, power consumption, and chip area of a logic circuit are the main targets of a designer. Most of the times, the designer sacrifices power consumption and chip area to improve delay for a given technology node. To overcome…
All practical OFDM systems require a prefix to eliminate inter-symbol interference at the receiver. Cyclic prefix (CP) and zero-padding are well-known prefix construction methods, the former being the most employed technique in practice due…
The irregular nature of memory accesses of graph workloads makes their performance poor on modern computing platforms. On manycore reconfigurable architectures (MRAs), in particular, even state-of-the-art graph prefetchers do not work well…
The proliferation of number of processing elements (PEs) in parallel computer systems, along with the use of more extensive parallelization of algorithms causes the interprocessor communications dominate VLSI chip space. This paper proposes…