Related papers: A Data Readout Approach for Physics Experiment
This work presents the design and preliminary performance of a highly-multiplexed superconducting detector readout. The readout system is implemented on the Xilinx ZCU111 RFSoC Evaluation Board. The current design uses 12% of the DSPs, 60%…
This paper proposes a diagnosis scheme aimed at reducing diagnosis time of distributed small embedded SRAMs (e-SRAMs). This scheme improves the one proposed in [A parallel built-in self-diagnostic method for embedded memory buffers, A…
FPGAs are increasingly utilized in data centers due to their capacity to exploit data parallelism in computationally intensive workloads. Furthermore, the processing of modern data center workloads requires moving vast amounts of data,…
Quantum computers have shown promise in improving algorithms in a variety of fields. The realization of these advancements is limited by the presence of noise and high error rates, which become prominent especially with increasing system…
Achieving low remote memory access latency remains the primary challenge in realizing memory disaggregation over Ethernet within the datacenters. We present EDM that attempts to overcome this challenge using two key ideas. First, while…
The average time $T$ required for high-fidelity readout of quantum states can be significantly reduced via a real-time adaptive decision rule. An adaptive decision rule stops the readout as soon as a desired level of confidence has been…
Region proposal is critical for object detection while it usually poses a bottleneck in improving the computation efficiency on traditional control-flow architectures. We have observed region proposal tasks are potentially suitable for…
High fidelity qubit readout is a cornerstone for quantum information protocols. In traditional superconducting qubit readout, a chain of microwave amplifiers and nonreciprocal components aid in detecting the qubit's state with tolerable…
Keyword Spotting nowadays is an integral part of speech-oriented user interaction targeted for smart devices. To this extent, neural networks are extensively used for their flexibility and high accuracy. However, coming up with a suitable…
Fast quantum data transmission faces several shortcomings such as the indistinguishability of some partly overlapping signals, the channel noises, and so on. Based on the encoded quantum data transmission protocol, an unconventional scheme…
Scalable, high-fidelity quantum-state readout remains a central challenge in the development of large-scale superconducting quantum processors. Conventional dispersive readout architectures depend on bulky isolators and external amplifiers,…
This paper discusses the present data acquisition system (DAQ) of the COMPASS experiment at CERN and presents development of a new DAQ. The new DAQ must preserve present data format and be able to communicate with FPGA cards. Parts of the…
CuboDAQ is a custom data acquisition system to read out SiPM-based detectors. It features electronic boards to digitize the SiPMs signal, an FPGA-based system-on-module board, the connectivity to transmit the data to a central server, and…
We present NetReduce, a novel RDMA-compatible in-network reduction architecture to accelerate distributed DNN training. Compared to existing designs, NetReduce maintains a reliable connection between end-hosts in the Ethernet and does not…
Parallel transmission, as defined in high-speed Ethernet standards, enables to use less expensive optoelectronics and offers backwards compatibility with legacy Optical Transport Network (OTN) infrastructure. However, optimal parallel…
It is usually infeasible to fit and train an entire large deep neural network (DNN) model using a single edge device due to the limited resources. To facilitate intelligent applications across edge devices, researchers have proposed…
The energy footprint of global data movement has surpassed 100 terawatt hours, costing more than 20 billion US dollars to the world economy. Depending on the number of switches, routers, and hubs between the source and destination nodes,…
Conventional wisdom holds that an efficient interface between an OS running on a CPU and a high-bandwidth I/O device should use Direct Memory Access (DMA) to offload data transfer, descriptor rings for buffering and queuing, and interrupts…
Among hardware accelerators for deep-learning inference, data flow implementations offer low latency and high throughput capabilities. In these architectures, each neuron is mapped to a dedicated hardware unit, making them well-suited for…
Edge computing is a promising solution for handling high-dimensional, multispectral analog data from sensors and IoT devices for applications such as autonomous drones. However, edge devices' limited storage and computing resources make it…