Related papers: FPGA design of a cdma2000 turbo decoder
The development of multicore architectures supporting parallel data processing has led to a paradigm shift, which affects communication systems significantly. This article provides a scalable parallel approach of an iterative LDPC decoder,…
This paper presents a partially parallel low-density parity-check (LDPC) decoder designed for the 5G New Radio (NR) standard. The design is using a multi-block parallel architecture with a flooding schedule. The decoder can support any code…
As the 50G optical access gradually matures, it is time to discuss Beyond 50G optical access. According to the evolution rules of optical access standards, Beyond 50G optical access data rate may achieve 200Gb/s. Direct detection faces…
Bitmap index is recognized as a promising candidate for online analytics processing systems, because it effectively supports not only parallel processing but also complex and multi-dimensional queries. However, bitmap index creation is a…
A new protograph-based framework for message passing (MP) decoding of low density parity-check (LDPC) codes with Hamming weight amplifiers (HWAs), which are used e.g. in the NIST post-quantum crypto candidate LEDAcrypt, is proposed. The…
The scan-based testing has been widely used as a Design-for-Test (DfT) mechanism for most recent designs. It has gained importance not only in manufacturing testing but also in online testing and debugging. However, the multiplexer-based…
The described multicoloring problem has direct applications in the context of wireless ad hoc and sensor networks. In order to coordinate the access to the shared wireless medium, the nodes of such a network need to employ some medium…
In the field of High Performance Computing, communications among processes represent a typical bottleneck for massively parallel scientific applications. Object of this research is the development of a network interface card with specific…
Convergence constrained power allocation (CCPA) in single carrier multiuser (MU) single-input multiple-output (SIMO) systems with turbo equalization is considered in this paper. In order to exploit full benefit of the iterative receiver,…
A discrete-time discrete-value pseudo-chaotic encoder/decoder system is presented. The pseudo-chaotic module is a 3D discrete version of the well-known Lorenz dynamical system. Scaling and biasing transformations as well as natural number…
In this paper, we report an encoding and decoding method for irregular-quasic-cyclic low-density parity-check (IR-QC-LDPC) codes with multi rates. The algorithm is applicable to parity-check matrices which have dual-diagonal parity…
A tridiagonal matrix algorithm (TDMA), Pipelined-TDMA, is developed for multi-GPU systems to resolve the scalability bottlenecks caused by the sequential structure of conventional divide-and-conquer TDMA. The proposed method pipelines…
We have developed a completely new type of general-purpose CCD data acquisition system which enables one to drive any type of CCD using any type of clocking mode. A CCD driver system widely used before consisted of an analog multiplexer…
In this paper we estimate the performance of 2*4 MIMO-MC-CDMA system using convolution code in MATLAB which highly reduces BER. MC-CDMA (Multi Carrier Code Division for Multiple Access) is a multiuser and multiple access system which is…
FPGA technology mapping is the process of implementing a hardware design expressed in high-level HDL (hardware design language) code using the low-level, architecture-specific primitives of the target FPGA. As FPGAs become increasingly…
Achieving high image quality is an important aspect in an increasing number of wireless multimedia applications. These applications require resource efficient error correction hardware to detect and correct errors introduced by the…
Diffusion transformers have demonstrated remarkable generation quality, albeit requiring longer training iterations and numerous inference steps. In each denoising step, diffusion transformers encode the noisy inputs to extract the…
Hardware acceleration has emerged as a key research topic for supporting computationally intensive signal processing and artificial intelligence applications in 6G research and development studies. This paper presents an RF Network on Chip…
Despite the increasing adoption of Field-Programmable Gate Arrays (FPGAs) in compute clouds, there remains a significant gap in programming tools and abstractions which can leverage network-connected, cloud-scale, multi-die FPGAs to…
This letter considers the transceiver design in frequency division duplex (FDD) massive multiple-input multiple-output (MIMO) orthogonal frequency division multiplexing (OFDM) systems for high-quality data transmission. We propose a novel…