Related papers: A Low-Voltage, Low-Power 4-bit BCD Adder, designed…
This paper investigates the design and performance of delayed bit-interleaved coded modulation (DBICM) with low-density parity-check (LDPC) codes. For Gray labeled square $M$-ary quadrature amplitude modulation (QAM) constellations, we…
A 6bit flash-ADC with 1.2GSps, wide analog bandwidth and low power, realized in a standard digital 0.13 $\mu$m CMOS copper technology is presented. Employing capacitive interpolation gives various advantages when designing for low power: no…
In this paper, a novel joint bit and power loading algorithm is proposed for orthogonal frequency division multiplexing (OFDM) systems operating in fading environments. The algorithm jointly maximizes the throughput and minimizes the…
Hybrid analog/digital architectures and receivers with low-resolution analog-to-digital converters (ADCs) are two low power solutions for wireless systems with large antenna arrays, such as millimeter wave and massive MIMO systems. Most…
The last few decades, a great deal of attention has been paid to low-voltage (LV) low-power (LP) integrated circuits design since the power consumption has become a critical issue. Among many techniques used for the design of LV LP analog…
We have developed a completely new type of general-purpose CCD data acquisition system which enables one to drive any type of CCD using any type of clocking mode. A CCD driver system widely used before consisted of an analog multiplexer…
A protograph-based low-density parity-check (LDPC) code design technique for bandwidth-efficient coded modulation is presented. The approach jointly optimizes the LDPC code node degrees and the mapping of the coded bits to the…
Adder cells using Gate Diffusion Technique (GDI) & PTL-GDI technique are described in this paper. GDI technique allows reducing power consumption, propagation delay and low PDP (power delay product) whereas Pass Transistor Logic (PTL)…
In present work a new XNOR gate using three transistors has been presented, which shows power dissipation of 550.7272$\mu$W in 0.35$\mu$m technology with supply voltage of 3.3V. Minimum level for high output of 2.05V and maximum level for…
This paper propose a decoder architecture for low-density parity-check convolutional code (LDPCCC). Specifically, the LDPCCC is derived from a quasi-cyclic (QC) LDPC block code. By making use of the quasi-cyclic structure, the proposed…
Now a days, power has become a primary consideration in hardware design, and is critical in computer systems especially for portable devices with high performance and more functionality. Clock-gating is the most common technique used for…
We present a power efficient clock-less fully asynchronous bit-serial Low Voltage Differential Signaling (LVDS) link with event-driven instant wake-up and self-sleep features, optimized for high speed inter-chip communication of…
In this work faster unsigned multiplication has been achieved by using a combination of High Performance Multiplication [HPM] column reduction technique and implementing a N-bit multiplier using 4 N/2-bit multipliers (recursive…
To reduce the leakage power of inactive (dark) silicon components, modern processor systems shut-off these components' power supply using low-leakage transistors, called power-gates. Unfortunately, power-gates increase the system's…
A protograph-based low-density parity-check (LDPC) code design technique for bandwidth-efficient coded modulation is presented. The approach jointly optimizes the LDPC code node degrees and the mapping of the coded bits to the…
Coded modulation is a key technique to increase the spectral efficiency of coherent optical communication systems. Two popular strategies for coded modulation are turbo trellis-coded modulation (TTCM) and bit-interleaved coded modulation…
A multiplierless pruned approximate 8-point discrete cosine transform (DCT) requiring only 10 additions is introduced. The proposed algorithm was assessed in image and video compression, showing competitive performance with state-of-the-art…
This paper describes a pipelined analog-to-digital converter (ADC) employing a power and area efficient architecture. The adjacent stages of a pipeline share operational amplifiers. In order to keep accuracy of the amplifiers in the first…
In this paper a low power and low area array multiplier with carry save adder is proposed. The proposed adder eliminates the final addition stage of the multiplier than the conventional parallel array multiplier. The conventional and…
For improving coarsely quantized decoding of LDPC codes, we propose a check node aware design of the variable node update. In contrast to previous works, we optimize the variable node to explicitly maximize the mutual information preserved…