Related papers: CMOS Low Power Cell Library For Digital Design
Complementary-metal-oxide-semiconductor (CMOS) is the most widely spread technology for integrated circuits fabrication. Each foundry offers different technology nodes that are characterized by the minimum feature size, which is the…
Side channel attacks are a major security concern for smart cards and other embedded devices. They analyze the variations on the power consumption to find the secret key of the encryption algorithm implemented within the security IC. To…
Silicon pixel sensors manufactured using commercial CMOS processes are promising instruments for high-energy particle physics experiments due to their high yield and proven radiation hardness. As one of the essential factors for the…
Nanopositioning techniques currently applied to characterize physical properties of materials interesting for applications at the microscopic scale rely on high-voltage electronic control circuits that should have the lowest possible noise…
Power electronics systems, widely used in various applications such as industrial automation, electric cars, and renewable energy, have the primary function of converting and controlling electrical power to the desired type of load. Despite…
A universal quantum computer~(QC), though promising ground breaking solutions to complex problems, still faces several challenges with respect to scalability. Current state-of-the-art QC use a great quantity of cables to connect the…
This paper presents the design and analysis of a wearable CMOS biosensor with three different designs of energy-resolution scalable time-based resistance to digital converters (RDC), targeted towards either minimizing the energy/conversion…
Due to market, there is flexibility in the price for power purchase by the utility. At the maximum loading condition the cost of power is high, hence conservation voltage reduction (CVR) is a useful technique in reducing power demand of the…
Optimization of power loss in soft magnetic components basis on the choice of the best technological parameters values. Therefore, the power losses have been measured in Somaloy 500 samples for a wide range of frequency and magnetic…
In recent years, scientific Complementary Metal Oxide Semiconductor (sCMOS) devices have been increasingly applied in X-ray detection, thanks to their attributes such as high frame rate, low dark current, high radiation tolerance and low…
The advance of autonomous Smart Sensor Networks and embedded systems for the Internet of Things, powered by photovoltaic energy harvesting, is severely limited by energy efficiency, especially in low-light environments. While Dynamic Power…
Quantum computing technology is maturing at a relentless pace, yet individual quantum bits are wired one by one. As quantum processors become more complex, they require efficient interfaces to deliver signals for control and readout while…
The design of cyber-physical systems (CPSs) faces various new challenges that are unheard of in the design of classical real-time systems. Power optimization is one of the major design goals that is witnessing such new challenges. The…
A robust power gating design using Graphene Nano-Ribbon Field Effect Transistors (GNRFET) is proposed using 16nm technology. The Power Gating (PG) structure is composed of GNRFET as a power switch and MOS power gated module. The proposed…
We present hardware/software techniques to intelligently regulate supply voltage and clock frequency of intermittently-computing devices. These devices rely on ambient energy harvesting to power their operation and small capacitors as…
The latest generation of transistors are nanoscale devices whose performance and reliability are limited by thermal noise in low-power applications. Therefore developing efficient methods to compute the voltage and current fluctuations in…
This paper presents and evaluates a novel method for generating power losses on transistors avoiding high currents. These could heat up the circuit tracks, affecting the accurate thermal modeling of the system. The proposed procedure is…
We present a scalable in-pixel processing architecture that can reduce the data throughput by 10X and consume less than 30 mW per megapixel at the imager frontend. Unlike the state-of-the-art (SOA) analog process-in-pixel (PIP) that…
This paper presents a fully-integrated CMOS voltage reference designed in a 90 nm process node using low voltage threshold (LVT) transistor models. The voltage reference leverages subthreshold operation and near-weak inversion…
Emerging memristor-based array architectures have been effectively employed in non-volatile memories and neuromorphic computing systems due to their density, scalability and capability of storing information. Nonetheless, to demonstrate a…