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Molecular communication has a key role to play in future medical applications, including detecting, analyzing, and addressing infectious disease outbreaks. Overcoming inter-symbol interference (ISI) is one of the key challenges in the…

Information Theory · Computer Science 2022-04-20 Xuan Chen , Miaowen Wen , Fei Ji , Yu Huang , Yuankun Tang , Andrew W. Eckford

We analyze and compare the characterization of a quantum device in terms of noise, transmitted bit-error-rate (BER) and mutual information, showing how the noise description is meaningful only for Gaussian channels. After reviewing the…

Quantum Physics · Physics 2015-06-26 G. M. D'Ariano , C. Macchiavello , L. Maccone

The reliability of memory devices is affected by radiation induced soft errors. Multiple cell upsets (MCUs) caused by radiation corrupt data stored in multiple cells within memories. Error correction codes (ECCs) are typically used to…

Hardware Architecture · Computer Science 2023-08-01 Sayan Tripathi , Jhilam Jana , Jaydeb Bhaumik

Modern FFT/NTT analytics, coded computation, and privacy-preserving ML interface routinely move polynomial frames across NICs, storage, and accelerators. However, even rare silent data corruption (SDC) can flip a few ring coefficients and…

Information Theory · Computer Science 2025-10-17 Baigang Chen , Dongfang Zhao

Conventional communication systems are mainly designed to reduce error rates and increase transmission rates, and therefore usually provide uniform protection to all transmitted messages. However, in intent-oriented applications, different…

Information Theory · Computer Science 2026-05-25 Qiming Lu , Shan Lu , Takaya Yamazato

The practical NAND flash memory suffers from various non-stationary noises that are difficult to be predicted. Furthermore, the data retention noise induced channel offset is unknown during the readback process. This severely affects the…

Information Theory · Computer Science 2019-07-10 Zhen Mei , Kui Cai , Xuan He

Two concatenated coding schemes based on fixed-rate Raptor codes are proposed for error control in NAND flash memory. One is geared for off-line recovery of uncorrectable pages and the other is designed for page error correction during the…

Information Theory · Computer Science 2013-12-23 Geunyeong Yu , Jaekyun Moon

Phase change memory (PCM) has recently emerged as a promising technology to meet the fast growing demand for large capacity memory in computer systems, replacing DRAM that is impeded by physical limitations. Multi-level cell (MLC) PCM…

Hardware Architecture · Computer Science 2017-11-27 Seyed Mohammad Seyedzadeh , Alex K. Jones , Rami Melhem

Ultra-low-power (ULP) Internet of Things (IoT) applications demand communication architectures with minimal energy consumption. Noise Modulation (NoiseMod) addresses this by encoding data through the statistical variance of a noise-like…

Quarter level cell (QLC) 3D NAND flash memory is emerging as the predominant storage solution in the era of artificial intelligence. QLC 3D NAND flash stores 4 bit per cell to expand the storage density, resulting in narrower read margins.…

Hardware Architecture · Computer Science 2025-11-04 Qianhui Li , Weiya Wang , Qianqi Zhao , Tong Qu , Jing He , Xuhong Qiang , Jingwen Hou , Ke Chen , Bao Zhang , Qi Wang

Increasing storage density exacerbates DRAM read disturbance, a circuit-level vulnerability exploited by system-level attacks. Unfortunately, existing defenses are either ineffective or prohibitively expensive. Efficient mitigation is…

Cryptography and Security · Computer Science 2024-08-28 Abdullah Giray Yağlıkçı

A key challenge in on-chip interconnect design is to scale up bandwidth while maintaining low latency and high area efficiency. 2D-meshes scale with low wiring area and congestion overhead; however, their end-to-end latency increases with…

Distributed, Parallel, and Cluster Computing · Computer Science 2025-08-05 Yichao Zhang , Zexin Fu , Tim Fischer , Yinrong Li , Marco Bertuletti , Luca Benini

In-memory computing is becoming a popular architecture for deep-learning hardware accelerators recently due to its highly parallel computing, low power, and low area cost. However, in-RRAM computing (IRC) suffered from large device…

Hardware Architecture · Computer Science 2022-05-10 Yu-Hsiang Chiang , Cheng En Ni , Yun Sung , Tuo-Hung Hou , Tian-Sheuan Chang , Shyh Jye Jou

The advent of massive ultra-reliable and low-latency communications (mURLLC) has introduced a critical class of time- and reliability-sensitive services within next-generation wireless networks. This shift has attracted significant research…

Systems and Control · Electrical Eng. & Systems 2024-10-16 Jingqing Wang , Wenchi Cheng , Wei Zhang

As DRAM scales in density and adopts 3D integration, raw fault rates increase and multi-bit errors are no longer rare. Such errors can severely impact Deep Neural Networks (DNNs): although DNNs tolerate small numerical perturbations, random…

Hardware Architecture · Computer Science 2026-05-07 Hanum Ko , Sangheum Yeon , Jong Hwan Ko , Jungrae Kim

Approaching ideal wire latency using a network-on-chip (NoC) is an important practical problem for many-core systems, particularly hundreds-cores. Although other researchers have focused on optimizing large meshes, bypassing or speculating…

Hardware Architecture · Computer Science 2016-07-28 Giorgos Passas

Communication over the binary erasure channel (BEC) using low-density parity-check (LDPC) codes and belief propagation (BP) decoding is considered. The average bit error probability of an irregular LDPC code ensemble after a fixed number of…

Information Theory · Computer Science 2009-05-23 Ryuhei Mori , Toshiyuki Tanaka , Kenta Kasai , Kohichi Sakaniwa

This paper presents performance analysis of an adaptive peak cancellation method to reduce the high peak-toaverage power ratio (PAPR) for OFDM systems, while keeping the out-of-band (OoB) power leakage as well as an in-band distortion power…

Signal Processing · Electrical Eng. & Systems 2020-07-02 Tomoya Kageyama , Osamu Muta , Haris Gacanin

Flash memory is a non-volatile computer memory comprising blocks of cells, wherein each cell can take on q different values or levels. While increasing the cell level is easy, reducing the level of a cell can be accomplished only by erasing…

Information Theory · Computer Science 2012-10-30 Eitan Yaakobi , Hessam Mahdavifar , Paul H. Siegel , Alexander Vardy , Jack K. Wolf

Developing ultra-low-energy superconducting computing and fault-tolerant quantum computing will require scalable superconducting memory. While conventional superconducting logic-based memory cells have facilitated early demonstrations,…

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