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CMOS VLSI technology is the most dominant integration methodology prevailing in the world today. Various signal-processing blocks are made using analog or digital design techniques in MOS VLSI. An important component is the Memory unit used…

A grid tied inverter converts DC voltage into AC voltage, while synchronizing it with the supply line phase and frequency. This paper presents an efficient, robust, and easy-to-implement grid tie mechanism. First, the grid tie mechanism was…

Phase clocks are synchronization tools that implement a form of logical time in distributed systems. For systems tolerating transient faults by self-repair of damaged data, phase clocks can enable reasoning about the progress of distributed…

Compute eXpress Link (CXL) is emerging as a promising memory interface technology. However, its performance characteristics remain largely unclear due to the limited availability of production hardware. Key questions include: What are the…

The fifth generation (5G) of the wireless communication networks supports wide diversity of service classes, leading to a highly dynamic uplink (UL) and downlink (DL) traffic asymmetry. Thus, dynamic time division duplexing (TDD) technology…

Grid-interactive power converters are normally synchronized to the grid using phase-locked loops (PLLs). The performance of the PLLs is affected by the non-ideal conditions in the sensed grid voltage such as harmonics, frequency deviations…

Transmitting polarization multiplexed carrier makes the receiver of a coherent system local oscillator-less and frequency offset-free. A polarization multiplexed carrier based self-homodyne (PMC-SH) system with an adaptive polarization…

Large-scale AI training and inference require hundreds of gigabytes to terabytes of DRAM with high peak to average utilization ratios, resulting in overprovisioning. In cloud computing, DRAM constitutes a significant share of the cost. Yet,…

Deep learning accelerators efficiently train over vast and growing amounts of data, placing a newfound burden on commodity networks and storage devices. A common approach to conserve bandwidth involves resizing or compressing data prior to…

This report presents the Prime Collective Communications Library (PCCL), a novel fault-tolerant collective communication library designed for distributed ML workloads over the public internet. PCCL introduces a new programming model that…

This paper presents design techniques for an energy-efficient multi-lane receiver (RX) with baud-rate clock and data recovery (CDR), which is essential for high-throughput low-latency communication in high-performance computing systems. The…

A key distinguishing feature of single flux quantum (SFQ) circuits is that each logic gate is clocked. This feature forces the introduction of path-balancing flip-flops to ensure proper synchronization of inputs at each gate. This paper…

In this paper, we implement a low-latency rapid-prototyping platform for signal processing based on software-defined radios (SDRs) and off-the-shelf PC hardware. This platform allows to evaluate a wide variety of algorithms in real-time…

In this article, a time-domain calibration procedure is proposed for pulsed Terahertz Integrated Circuits (TIC) used in on-chip applications, where the conventional calibration methods are not applicable. The proposed post-detection method…

Quantum error mitigation (QEM) is critical for harnessing the potential of near-term quantum devices. Particularly, QEM protocols can be designed based on machine learning, where the mapping between noisy computational outputs and ideal…

A clock synchronizing circuit for repeaterless low swing interconnects is presented in this paper. The circuit uses a delay locked loop (DLL) to generate multiple phases of the clock, of which the one closest to the center of the eye is…

This paper presents a novel strategy for the synchronization of grid-following Voltage Source Converters (VSCs) in power systems with low rotational inertia. The proposed synchronization unit is based on emulating the physical properties of…

Phase-locked loops (PLL), Costas loops and other synchronizing circuits are featured by the presence of a nonlinear phase detector, described by a periodic nonlinearity. In general, nonlinearities can cause complex behavior of the system…

Large language models (LLMs) training or inference across multiple nodes introduces significant pressure on GPU memory and interconnect bandwidth. The Compute Express Link (CXL) shared memory pool offers a scalable solution by enabling…

Scalable coherent control hardware for quantum information platforms is rapidly growing in priority as their number of available qubits continues to increase. As these systems scale, more calibration steps are needed, leading to challenges…