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Today every circuit has to face the power consumption issue for both portable device aiming at large battery life and high end circuits avoiding cooling packages and reliability issues that are too complex. It is generally accepted that…

Hardware Architecture · Computer Science 2010-07-15 C. N. Marimuthu , P. Thangaraj , Aswathy Ramesan

Quantum circuits of many qubits are extremely difficult to realize; thus, the number of qubits is an important metric in a quantum circuit design. Further, scalable and reliable quantum circuits are based on Clifford + T gates. An efficient…

Quantum Physics · Physics 2017-06-19 Edgard Muñoz-Coreas , Himanshu Thapliyal

Transformer models have revolutionized AI tasks, but their large size hinders real-world deployment on resource-constrained and latency-critical edge devices. While binarized Transformers offer a promising solution by significantly reducing…

Machine Learning · Computer Science 2025-05-13 Yuhao Ji , Chao Fang , Shaobo Ma , Haikuo Shao , Zhongfeng Wang

This paper presents an approximate signed multiplier architecture that incorporates a sign-focused compressor, specifically designed for edge detection applications in machine learning and signal processing. The multiplier incorporates two…

Hardware Architecture · Computer Science 2025-10-28 L. Hemanth Krishna , Srinivasu Bodapati , Sreehari Veeramachaneni , BhaskaraRao Jammu , Noor Mahammad Sk

We propose an optimization method for the automatic design of approximate multipliers, which minimizes the average error according to the operand distributions. Our multiplier achieves up to 50.24% higher accuracy than the best reproduced…

Hardware Architecture · Computer Science 2023-10-26 Su Zheng , Zhen Li , Yao Lu , Jingbo Gao , Jide Zhang , Lingli Wang

The idle time of personal computers has increased steadily due to the generalization of computer usage and cloud computing. Clustering research aims at utilizing idle computer resources for processing a variable workload on a large number…

Distributed, Parallel, and Cluster Computing · Computer Science 2021-01-25 Geunsik Lim , Minho Lee , R. J. W. E. Lahaye , Young Ik Eom

Wallace tree multipliers are a parallel digital multiplier architecture designed to minimize the worst-case time complexity of the circuit depth relative to the input size [1]. In particular, it seeks to perform long multiplication in the…

Hardware Architecture · Computer Science 2025-09-12 Ayan Biswas , Jimmy Jin

Bitwise operations are an important component of modern day programming. Many widely-used data structures (e.g., bitmap indices in databases) rely on fast bitwise operations on large bit vectors to achieve high performance. Unfortunately,…

Existing binary Transformers are promising in edge deployment due to their compact model size, low computational complexity, and considerable inference accuracy. However, deploying binary Transformers faces challenges on prior processors…

Hardware Architecture · Computer Science 2024-07-16 Yuhao Ji , Chao Fang , Zhongfeng Wang

Distributed network optimization has been studied for well over a decade. However, we still do not have a good idea of how to design schemes that can simultaneously provide good performance across the dimensions of utility optimality,…

Networking and Internet Architecture · Computer Science 2017-07-19 Sinong Wang , Ness Shroff

Multiplication is a fundamental operation in many applications, and multipliers are widely adopted in various circuits. However, optimizing multipliers is challenging due to the extensive design space. In this paper, we propose a multiplier…

Hardware Architecture · Computer Science 2024-12-30 Dongsheng Zuo , Jiadong Zhu , Yikang Ouyang , Yuzhe Ma

There has been considerable research into improving Fast Fourier Transform (FFT) performance through parallelization and optimization for specialized hardware. However, even with those advancements, processing of very large files, over 1TB…

Distributed, Parallel, and Cluster Computing · Computer Science 2014-07-28 Rostislav Tsiomenko , Bradley S. Rees

Matrix multiplication is a foundational operation in scientific computing and machine learning, yet its computational complexity makes it a significant bottleneck for large-scale applications. The shift to parallel architectures, primarily…

Distributed, Parallel, and Cluster Computing · Computer Science 2025-07-30 Mufakir Qamar Ansari , Mudabir Qamar Ansari

We present efficient circuits for the addition of binary numbers. We assume that we are given arrival times for all input bits and optimize the delay of the circuits, i.e.\ the time when the last output bit is computed. This contains the…

Logic in Computer Science · Computer Science 2024-09-11 Ulrich Brenner , Benjamin David Görg

Deploying mixed-precision neural networks on edge devices is friendly to hardware resources and power consumption. To support fully mixed-precision neural network inference, it is necessary to design flexible hardware accelerators for…

Hardware Architecture · Computer Science 2025-02-04 Liang Zhao , Kunming Shao , Fengshi Tian , Tim Kwang-Ting Cheng , Chi-Ying Tsui , Yi Zou

In this paper a low power and low area array multiplier with carry save adder is proposed. The proposed adder eliminates the final addition stage of the multiplier than the conventional parallel array multiplier. The conventional and…

Hardware Architecture · Computer Science 2011-12-01 Nirlakalla Ravi , A. Satish , T. Jayachandra Prasad , T. Subba Rao

We leverage the Multiplicative Weight Update (MWU) method to develop a decentralized algorithm that significantly improves the performance of dynamic time division duplexing (D-TDD) in small cell networks. The proposed algorithm adaptively…

Information Theory · Computer Science 2024-02-09 Jiaqi Zhu , Nikolaos Pappas , Howard H. Yang

Montgomery modular multiplication is widely-used in public key cryptosystems (PKC) and affects the efficiency of upper systems directly. However, modulus is getting larger due to the increasing demand of security, which results in a heavy…

Cryptography and Security · Computer Science 2026-03-17 Yuxuan Zhang , Hua Guo , Chen Chen , Yewei Guan , Xiyong Zhang , Zhenyu Guan

This paper describes a new accumulate-and-add multiplication algorithm. The method partitions one of the operands and re-combines the results of computations done with each of the partitions. The resulting design turns-out to be both…

Mathematical Software · Computer Science 2011-04-11 Byungchun Chung , Sandra Marcello , Amir-Pasha Mirbaha , David Naccache , Karim Sabeg

We study the problem of computing matrix chain multiplications in a distributed computing cluster. In such systems, performance is often limited by the straggler problem, where the slowest worker dominates the overall computation latency.…

Information Theory · Computer Science 2026-01-14 Jesús Gómez-Vilardebò