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In this paper, the acceleration of algorithms using a design of a field programmable gate array (FPGA) as a prototype of a static dataflow architecture is discussed. The static dataflow architecture using operators interconnected by…

Hardware Architecture · Computer Science 2015-03-13 Jorge Luiz e Silva , Joelmir Jose Lopes , Bruno de Abreu Silva , Antonio Carlos Fernandes da Silva

Transformers are central to advances in artificial intelligence (AI), excelling in fields ranging from computer vision to natural language processing. Despite their success, their large parameter count and computational demands challenge…

Hardware Architecture · Computer Science 2025-03-10 Qunyou Liu , Marina Zapater , David Atienza

FPGAs have found increasing adoption in data center applications since a new generation of high-level tools have become available which noticeably reduce development time for FPGA accelerators and still provide high quality of results.…

Distributed, Parallel, and Cluster Computing · Computer Science 2020-06-15 Marius Meyer , Tobias Kenter , Christian Plessl

FPGA programming is more complex as compared to Central Processing Units (CPUs) and Graphics Processing Units (GPUs). The coding languages to define the abstraction of Register Transfer Level (RTL) in High Level Synthesis (HLS) for FPGA…

Hardware Architecture · Computer Science 2024-10-04 Rourab Paul , Alberto Ottimo , Marco Danelutto

We present Calyx, a new intermediate language (IL) for compiling high-level programs into hardware designs. Calyx combines a hardware-like structural language with a software-like control flow representation with loops and conditionals.…

Programming Languages · Computer Science 2021-11-17 Rachit Nigam , Samuel Thomas , Zhijing Li , Adrian Sampson

High level programming languages and GPU accelerators are powerful enablers for a wide range of applications. Achieving scalable vertical (within a compute node), horizontal (across compute nodes), and temporal (over different generations…

The GPU as a digital signal processing accelerator for cloud RAN is investigated. A new design for a 5G NR low density parity check code decoder running on a GPU is presented. The algorithm is flexibly adaptable to GPU architecture to…

Networking and Internet Architecture · Computer Science 2020-09-14 Jonathan Ling , Paul Cautereels

C/C++/OpenCL-based high-level synthesis (HLS) becomes more and more popular for field-programmable gate array (FPGA) accelerators in many application domains in recent years, thanks to its competitive quality of results (QoR) and short…

Hardware Architecture · Computer Science 2021-05-07 Yuze Chi , Licheng Guo , Jason Lau , Young-kyu Choi , Jie Wang , Jason Cong

Efficient parallelization of algorithms on general-purpose GPUs is essential in many areas today. However, it is a non-trivial task for software engineers to utilize GPUs to improve the performance of high-level programs in general.…

Programming Languages · Computer Science 2024-07-09 Lars Hummelgren , John Wikman , Oscar Eriksson , Philipp Haller , David Broman

Multiphase compressible flows are often characterized by a broad range of space and time scales. Thus entailing large grids and small time steps, simulations of these flows on CPU-based clusters can thus take several wall-clock days.…

Graph Neural Networks (GNNs) have shown great superiority on non-Euclidean graph data, achieving ground-breaking performance on various graph-related tasks. As a practical solution to train GNN on large graphs with billions of nodes and…

Machine Learning · Computer Science 2024-09-24 Zeyu Zhu , Peisong Wang , Qinghao Hu , Gang Li , Xiaoyao Liang , Jian Cheng

Large-scale floating-point matrix multiplication is a fundamental kernel in many scientific and engineering applications. Most existing work only focus on accelerating matrix multiplication on FPGA by adopting a linear systolic array. This…

Hardware Architecture · Computer Science 2018-03-13 Junzhong Shen , Yuran Qiao , You Huang , Mei Wen , Chunyuan Zhang

FastFlow is a structured parallel programming framework targeting shared memory multicores. Its layered design and the optimized implementation of the communication mechanisms used to implement the FastFlow streaming networks provided to…

Distributed, Parallel, and Cluster Computing · Computer Science 2012-04-25 Marco Aldinucci , Marco Danelutto , Massimo Torquati

This paper describes neural-fortran, a parallel Fortran framework for neural networks and deep learning. It features a simple interface to construct feed-forward neural networks of arbitrary structure and size, several activation functions,…

Machine Learning · Computer Science 2019-03-26 Milan Curcic

We present a technique for automatically transforming kernel-based computations in disparate, nested loops into a fused, vectorized form that can reduce intermediate storage needs and lead to improved performance on contemporary hardware.…

Performance · Computer Science 2017-10-25 Jason Sewall , Simon J. Pennycook

To enable heterogeneous computing systems with autonomous programming and optimization capabilities, we propose a unified, end-to-end, programmable graph representation learning (PGL) framework that is capable of mining the complexity of…

Machine Learning · Computer Science 2022-04-27 Yao Xiao , Guixiang Ma , Nesreen K. Ahmed , Mihai Capota , Theodore Willke , Shahin Nazarian , Paul Bogdan

Pretrained Transformers achieve state-of-the-art performance in various code-processing tasks but may be too large to be deployed. As software development tools often incorporate modules for various purposes which may potentially use a…

Computation and Language · Computer Science 2022-12-13 Shamil Ayupov , Nadezhda Chirkova

Increasing demands for computing power also propel the need for energy-efficient SoC accelerator architectures. One class for such accelerators are so-called processor arrays, which typically integrate a two-dimensional mesh of…

Hardware Architecture · Computer Science 2025-02-28 Dominik Walter , Marita Halm , Daniel Seidel , Indrayudh Ghosh , Christian Heidorn , Frank Hannig , Jürgen Teich

Compiler optimizations, usually expressed as rewrites on program graphs, are a core part of all modern compilers. However, even production compilers have bugs, and these bugs are difficult to detect and resolve. The problem only becomes…

Programming Languages · Computer Science 2014-07-31 William Mansky , Dennis Griffith , Elsa L. Gunter

Fortran is the lingua franca of HPC code development and as such it is crucial that we as a community have open source Fortran compilers capable of generating high performance executables. Flang is LLVM's Fortran compiler and leverages MLIR…

Distributed, Parallel, and Cluster Computing · Computer Science 2024-09-30 Nick Brown