Related papers: Development of front-end readout electronics for s…

We present our latest ASIC, which is used for the readout of Cadmium Telluride double-sided strip detectors (CdTe DSDs) and high spectroscopic imaging. It is implemented in a 0.35 um CMOS technology (X-Fab XH035), consists of 64 readout…

A 64-channel mixed-mode ASIC, suitable for particle detectors of large dynamic range and high capacitance up to hundreds of pF, is presented here. Each channel features an analogue front-end for signal amplification and filtering, and a…

Multiple application-specific integrated circuits (ASIC) are required for the detectors if their readout channels are larger than that of ASIC channels. For a system with such a readout scheme, there is a need to configure channels among…

A complete dedicated electronics, from front-end to back-end, was developed to instrument a MIMAC prototype. A front end ASIC able to monitor 64 strips of pixels and to provide their individual "Time Over Threshold" information has been…

We developed a new front-end application specific integrated circuit (ASIC) for the upgrade of the Maia x-ray microprobe. The ASIC instruments 32 configurable front-end channels that perform either positive or negative charge amplification,…

Compact multi-channel radiation detectors rely on low noise front-end application specific integrated circuits (ASICs) to achieve high spectral resolution. Here, a new ASIC developed to readout virtual Frisch-grid cadmium zinc telluride…

An Application Specific Integrated Circuit (ASIC), called RIGEL, designed for the sparse readout of a Silicon Pixel Drift Detector (PixDD) for space applications is presented.The low leakage current (less than 1 pA at +20 {\deg}C) and anode…

This paper presents the NSX front-end ASIC, being developed to read charge signals from the HEMA and WFM X-ray detectors for the STROBE-X mission. The ASIC reads out signals from up to 64 anodes of linear Silicon Drift Detectors (SDDs).…

Modern PET scanners based on scintillating crystals use solid state photo detectors for light readout. The small area of these devices is beneficial for spatial resolution, but also leads to a large number of electronic channels to be read…

The detector readout architecture introduced in this paper is intended for small to medium size physics experiments that have moderate bandwidth needs, and applications that require an ultimately low background radioactivity for the parts…

We develop the vertex detector for the international linear collider (ILC) using the FPCCD (Fine Pixel CCD), whose pixel size is 5 x 5 um2. Together with the FPCCD sensor, a prototype of the readout ASIC was developed in 2008. The readout…

A front end ASIC has been designed to equip the {\mu}TPC prototype developed for the MIMAC project, which requires 3D reconstruction of low energy particle tracks in order to perform directional detection of galactic Dark Matter. Each ASIC…

For the High-Luminosity phase of LHC, the ATLAS experiment is proposing the addition of a High Granularity Timing Detector (HGTD) in the forward region to mitigate the effects of the increased pile-up. The chosen detection technology is Low…

A scalable readout system (SRS) is designed to provide a general solution for different micro-pattern gas detectors. The system mainly consists of three kinds of modules: the ASIC card, the Adapter card and the Front-End Card (FEC). The…

In the context of the Silicon tracking for a Linear Collider (SiLC) R&D collaboration, a highly compact mixed-signal chip has been designed in 130nm CMOS technology intended to read Silicon strip detectors for the experiments at the future…

We report on progress in the development of the LSTFE2 prototype front-end ASIC geared towards the readout of silicon microstrip sensors in a Linear Collider detector. We also discuss progress in the design of the back-end digital…

A new TDC-chip is under development for the COMPASS experiment at CERN. The ASIC, which exploits the 0.6 micrometer CMOS sea-of-gate technology, will allow high resolution time measurements with digitization of 75 ps, and an unprecedented…

One of candidates for the International Linear Collider(ILC)'s vertex detector is the Fine Pixel CCD (FPCCD) with a pixel size of 5 \times 5 (\mum^2). Sensor and readout systems are currently being studied and prototypes have been…

The SALSA chip is a future readout ASIC foreseen for the MPGD detectors, developed in the framework of the EIC collider project, to equip the MPGD trackers of the EPIC experiment. It is designed to be versatile, to be adapted to other…

The present article introduces a novel ASIC architecture, designed in the context of the ATLAS Tile Calorimeter upgrade program for the High-Luminosity phase of the Large Hadron Collider at CERN. The architecture is based on…