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Gate tunable p-type multilayer tin mono-sulfide (SnS) field-effect transistor (FET) devices with SnS thickness between 50 and 100 nm were fabricated and studied to understand their performances. The devices showed anisotropic inplane…
Modern microelectronic systems require long term operational stability, necessitating precise reliability models to predict device lifecycles and identify governing failure mechanisms. This is particularly critical for high power GaN…
Spin-based logic devices could operate at very high speed with very low energy consumption and hold significant promise for quantum information processing and metrology. Here, an in-house developed, experimentally verified, ensemble…
Heterogeneous networks (HetNets) with offloading is considered as an effective way to meet the high data rate demand of future wireless service. However, the offloaded users suffer from strong inter-tier interference, which reduces the…
We present tools and methods to generalize parity compilation to digital quantum computing devices with arbitrary connectivity graphs and construct circuit implementations for the constraint Hamiltonian of higher-order constrained binary…
This work proposes an efficient parallel algorithm for non-monotone submodular maximization under a knapsack constraint problem over the ground set of size $n$. Our algorithm improves the best approximation factor of the existing parallel…
Using the tip of a scanning probe microscope as a local electrostatic gate gives access to real space information on electrostatics as well as charge transport at the nanoscale, provided that the tip-induced electrostatic potential is well…
We examine the detailed scenario for implementing n-control-qubit Toffoli gates and select gates on ion-trap quantum computers, especially those that shuttle ions into interaction zones. We determine expected performance of these gates with…
Three-dimensional integration technologies such as flip-chip bonding are a key prerequisite to realize large-scale superconducting quantum processors. Modular architectures, in which circuit elements are spread over multiple chips, can…
Hybrid analog-digital (A/D) transceivers designed for millimeter wave (mmWave) systems have received substantial research attention, as a benefit of their lower cost and modest energy consumption compared to their fully-digital…
In this work, we simulate the expected device performance and the scaling perspectives of Carbon nanotube Field Effect Transistors (CNT-FETs), with doped source and drain extensions. The simulations are based on the self-consistent solution…
We report the first experimental demonstration that interface microstructure limits diffusive electrical spin injection efficiency across heteroepitaxial interfaces. A theoretical treatment shows that the suppression of spin injection due…
Nanoscale devices are being extensively studied for their tunable electronic and optical properties, but the influence of impurities and defects is amplified at these length scales and can lead to poorly understood variations in…
Design and implementation of an optimal and robust single-loop voltage controller is proposed for single-phase grid forming voltage source inverter (VSI). The objective of the proposed controller is to have good reference tracking and…
Fault tolerance overhead of high performance computing (HPC) applications is becoming critical to the efficient utilization of HPC systems at large scale. HPC applications typically tolerate fail-stop failures by checkpointing. Another…
We propose a pilot-data transmission overlay scheme for multipair massive multiple-input multiple-output (MIMO) relaying systems employing either half- or full-duplex (HD or FD) communications at the relay station (RS). In the proposed…
To increase the power of a trapped ion quantum information processor, the qubit number, gate speed, and gate fidelity must all increase. All three of these parameters are influenced by the trapping field which in turn depends on the…
Convolutional Neural Networks (CNNs) are crucial in various applications, but their deployment on resource-constrained edge devices poses challenges. This study presents the Sum-of-Products (SOP) units for convolution, which utilize…
Using 2-D self-consistent ballistic quantum transport simulations, we investigate the short-channel behavior of graphene field-effect transistors and its impact on the device transconductance and subsequently the intrinsic cut-off frequency…
In this paper, we propose TAPA, an end-to-end framework that compiles a C++ task-parallel dataflow program into a high-frequency FPGA accelerator. Compared to existing solutions, TAPA has two major advantages. First, TAPA provides a set of…