Related papers: Low Power Shift and Add Multiplier Design
In this paper power allocation in a cellular network, which transmitter uses massive multiple inputs multiple outputs (MIMO) system was studied. As circuit power consumption is increased by the number of antenna in transmitter and users,…
The high spectral efficiency of massive MIMO (Multiple Input Multiple Output) is mainly achieved through the exploitation of spatial multiplexing, i.e. by using a high number of MIMO layers that are applied simultaneously to many users. The…
Data movement is the dominating factor affecting performance and energy in modern computing systems. Consequently, many algorithms have been developed to minimize the number of I/O operations for common computing patterns. Matrix…
We analyze a physically motivated fine-grained mesh-connected computer model, assuming that a word of information takes a fixed area and that it takes unit time and unit energy to move a word unit distance. This is a representation of…
In massive MIMO systems, fully digital precoding offers high performance but has significant implementation complexity and energy consumption, particularly at millimeter frequencies and beyond. Hybrid analog-digital architectures provide a…
Quantum circuits of many qubits are extremely difficult to realize; thus, the number of qubits is an important metric in a quantum circuit design. Further, scalable and reliable quantum circuits are based on Clifford + T gates. An efficient…
The implementation of a quaternary 1-digit adder composed of a 2-bit binary adder, quaternary to binary decoders and binary to quaternary encoders is compared with several recent implementations of quaternary adders. This simple…
This thesis develops signal-processing algorithms and implementation schemes under constraints of minimal parallelism and memory space, with the goal of improving energy efficiency of low-power computing hardware. We propose (i) a…
With the surge of the powerful quantum computer, lattice-based cryptography proliferated the latest cryptography hardware implementation due to its resistance against quantum computers. Among the computational blocks of lattice-based…
In this paper, we combine communication-theoretic laws with known, practically verified results from circuit theory. As a result, we obtain closed-form theoretical expressions linking fundamental system design and environment parameters…
Multiplication is a core operation in modern neural network (NN) computations, contributing significantly to energy consumption. The linear-complexity multiplication (L-Mul) algorithm is specifically proposed as an approximate…
Reducing power consumption in AI accelerators is increasingly important. Approximate computing can reduce power consumption while keeping the accuracy loss small. Since multipliers are power-hungry components in AI models, this paper…
Existing works on Cell-Free Massive MIMO primarily focus on optimising system throughput and energy efficiency under high-traffic scenarios with only a limited focus on variable user demand as required by higher network layers.…
In this work, we study massive multiple-input multiple-output (MIMO) precoders optimizing power consumption while achieving the users' rate requirements. We first characterize analytically the solutions for narrowband and wideband systems…
Printed Electronics (PE) provide a flexible, cost-efficient alternative to silicon for implementing machine learning (ML) circuits, but their large feature sizes limit classifier complexity. Leveraging PE's low fabrication and NRE costs,…
In this paper, we explore reduced-connectivity radio frequency (RF) switching networks for reducing the analog hardware complexity and switching power losses in antenna selection (AS) systems. In particular, we analyze different hardware…
This paper presents an energy-efficient downlink precoding scheme with the objective of maximizing system energy efficiency in a multi-cell massive MIMO system. The proposed precoding design jointly considers the issues of power control,…
There are increasing number of works addressing the design challenges of fast, scalable solutions for the growing number of new type of applications. Recently, many of the solutions aimed at improving processing element capabilities to…
Researchers and designers are facing problems with memory and power walls, considering the pervasiveness of Von-Neumann architecture in the design of processors and the problems caused by reducing the dimensions of deep sub-micron…
This paper presents a low-power cache architecture based on the series interconnection of conventional 6-transistor static random-access memory (6T SRAM) cells. The proposed approach aims to reduce leakage power in SRAM-based cache memories…