Related papers: A 8 bits Pipeline Analog to Digital Converter Desi…
In most digital-to-time converter (DTC) based applications, apart from maintaining low integral non-linearity (INL), it is also required of the system to achieve a wide frequency translation range. To achieve this performance, we present a…
The design of a high-precision time-to-digital converter (TDC) based on a multiphase clock implemented using a single field-programmable gate array is discussed in this paper. The TDC can increase the resolution of the measurement by using…
The signal bandwidth of Digital to Analog Converters based on Sigma Delta Modulation is limited by speed constrains. Time-Interleaving allows coping with complexity vs. speed by replacing the original architecture by M parallel paths. These…
Analog multiplexing appears to be a promising solution for modern transmitters, where speed is the primary limitation. The objective is the development of a low-cost solution to compare different digital to analog (DAC) schemes. In…
The low-resolution analog-to-digital convertor (ADC) is a promising solution to significantly reduce the power consumption of radio frequency circuits in massive multiple-input multiple-output (MIMO) systems. In this letter, we investigate…
This paper presents a 17 bit analogue-to-digital converter that incorporates mismatch and quantisation noise-shaping techniques into an energy-saving 10 bit successive approximation quantiser to increase the dynamic range by another 42 dB.…
Flash Analog to Digital Convertor (FADC) is frequently used in nuclear and particle physics experiments, often as the major component in big multi-channel systems. The large data volume makes the optimization of operating parameters…
Motivated by the demand for energy-efficient communication solutions in the next generation cellular network, a mixed-ADC architecture for massive multiple input multiple output (MIMO) systems is proposed, which differs from previous works…
Analog Compute-in-Memory (CiM) accelerators are increasingly recognized for their efficiency in accelerating Deep Neural Networks (DNN). However, their dependence on Analog-to-Digital Converters (ADCs) for accumulating partial sums from…
Partial resonance high frequency AC link converters are recognized to provide soft-switching, single-stage power conversion. They are highly reliable due to elimination of DC capacitors. Previous work has focused on proof of concept…
Improving the power efficiency and spectral efficiency of communication systems has been one of the major research goals over the recent years. However, there is a tradeoff in achieving both goals at the same time. In this work, we consider…
Direct current (DC) converters play an essential role in electronic circuits. Conventional high-efficiency DC voltage converters, especially step-up type, rely on switch-mode operation, where energy is periodically stored within and…
In this paper, we propose an analog pixel differencing circuit for differentiating pixels between frames directly from CMOS pixels. The analog information processing at sensor is a topic of growing appeal to develop edge AI devices. The…
Reservoir computing is an information processing technique, derived from the theory of neural networks, which is easy to implement in hardware. Several reservoir computer hardware implementations have been realized recently with performance…
Analog in-memory computing (AIMC) is an energy-efficient alternative to digital architectures for accelerating machine learning and signal processing workloads. However, its energy efficiency is limited by the high energy cost of the column…
In this work, we investigate dynamic oversampling techniques for large-scale multiple-antenna systems equipped with low-cost and low-power 1-bit analog-to-digital converters at the base stations. To compensate for the performance loss…
In this paper, we propose an architecture for FPGA emulation of mixed-signal systems that achieves high accuracy at a high throughput. We represent the analog output of a block as a superposition of step responses to changes in its analog…
Wireless systems with inband full-duplex transceiver typically require multiple lines of defense against the effect of harsh self-interference, specifically, to avoid saturation of the analog-to-digital converter (ADC) in the receiver. We…
The aim of this study is to design and evaluate a simple free running Analog-Digital Converter (ADC) based on the Field Programmable Gate Array (FPGA) device to accomplish the energy and position readout of the silicon photomultiplier…
This paper proposes a novel foreground linearization scheme for a high-speed CS-DAC. The technique leverages neural networks (NNs) to derive a LUT that maps the inverse of the DAC transfer characteristic onto the input codes. The algorithm…