Related papers: Very Fast Chip-level Thermal Analysis
The athermal quasistatic deformation method provides an elegant solution to overcome the limitation of short time spans in molecular simulations. It provides overdamped conditions, allowing for the extraction of purely structural responses…
Thermal analysis provides deeper insights into electronic chips behavior under different temperature scenarios and enables faster design exploration. However, obtaining detailed and accurate thermal profile on chip is very time-consuming…
We introduce a high-performance virtual machine (VM) written in a numerically fast language like Fortran or C to evaluate very large expressions. We discuss the general concept of how to perform computations in terms of a VM and present…
Despite temperature rise being a first-order design constraint, traditional thermal estimation techniques have severe limitations in modeling critical aspects affecting the temperature in modern-day chips. Existing thermal modeling…
In a multiprocessor system on chip (MPSoC) IC the processor is one of the highest heat dissipating devices. The temperature generated in an IC may vary with floor plan of the chip. This paper proposes an integration and thermal analysis…
Thermal aware routing and placement algorithms are important in industry. Currently, there are reasonably fast Green's function based algorithms that calculate the temperature distribution in a chip made from a stack of different materials.…
We propose HAMSI (Hessian Approximated Multiple Subsets Iteration), which is a provably convergent, second order incremental algorithm for solving large-scale partially separable optimization problems. The algorithm is based on a local…
Besides the lot of advantages offered by the 3D stacking of devices in an integrated circuit there is a chance of device damage due to rise in peak temperature value. Hence, in order to make use of all the potential benefits of the vertical…
Interconnect is one of the main performance determinant of modern integrated circuits (ICs). The new technology of vertical ICs places circuit blocks in the vertical dimension in addition to the conventional horizontal plane. Compared to…
The SLUSCHI (Solid and Liquid in Ultra Small Coexistence with Hovering Interfaces) automated package, with interface to the first-principles code VASP (Vienna Ab initio Simulation Package), was developed by us for efficiently determining…
3D integration technologies are seeing widespread adoption in the semiconductor industry to offset the limitations and slowdown of two-dimensional scaling. High-density 3D integration techniques such as face-to-face wafer bonding with…
Thermally aware design of 2.5D and 3D advanced packaging systems will require fast, accurate, and powerful thermal analysis of chiplets, stacks, and packages. These systems contain multiple materials with non-linear heat transfer properties…
Witnessing the advancing scale and complexity of chip design and benefiting from high-performance computation technologies, the simulation of Very Large Scale Integration (VLSI) Circuits imposes an increasing requirement for acceleration…
RISC-V GPUs present a promising path for supporting GPU applications. Traditionally, GPUs achieve high efficiency through the SPMD (Single Program Multiple Data) programming model. However, modern GPU programming increasingly relies on…
The increasing power densities and intricate heat dissipation paths in advanced 2.5D/3D chiplet systems necessitate thermal modeling frameworks that deliver detailed thermal maps with high computational efficiency. Traditional compact…
Accurate on-chip temperature sensing is critical for the optimal performance of modern CMOS integrated circuits (ICs), to understand and monitor localized heating around the chip during operation. The development of quantum computers has…
In analog neuromorphic chips, designers can embed computing primitives in the intrinsic physical properties of devices and circuits, heavily reducing device count and energy consumption, and enabling high parallelism, because all devices…
Numerical simulation of the laser powder bed fusion (LPBF) procedure for additive manufacturing (AM) is difficult due to the presence of multiple scales in both time and space, ranging from the part scale (order of millimeters/seconds) to…
Partitioning graphs into blocks of roughly equal size such that few edges run between blocks is a frequently needed operation when processing graphs on a parallel computer. When a topology of a distributed system is known an important task…
As transistor counts in a single chip exceed tens of billions, the complexity of RTL-level simulation and verification has grown exponentially, often extending simulation campaigns to several months. In industry practice, RTL simulation is…