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Secure Function Evaluation (SFE) has received recent attention due to the massive collection and mining of personal data, but remains impractical due to its large computational cost. Garbled Circuits (GC) is a protocol for implementing SFE…

Cryptography and Security · Computer Science 2019-12-05 Xin Fang , Stratis Ioannidis , Miriam Leeser

As the deployment of artifical intelligence (AI) algorithms at edge devices becomes increasingly prevalent, enhancing the robustness and reliability of autonomous AI-based perception and decision systems is becoming as relevant as precision…

Computer Vision and Pattern Recognition · Computer Science 2024-12-06 Jon Gutiérrez-Zaballa , Koldo Basterretxea , Javier Echanobe

Fault tolerance is increasingly being use to design Dependable Digital Systems (DDS), which refers to the capability of a system to keep performing its intended functions in existence of faults. DDS are typically used in Safety-critical…

Hardware Architecture · Computer Science 2021-04-20 Farah Natiq Kassab bashi , Shawkat S Khairullah

In this paper, a fault-tolerant approach to mitigate transient and permanent faults of arithmetic and logic operations of embedded processors called FT-EALU is proposed. In this method, each operation is replicated in time and the derived…

Hardware Architecture · Computer Science 2022-04-05 Athena Abdi , Sina Shahoveisi

Specialized hardware accelerators have been designed and employed to maximize the performance efficiency of Spiking Neural Networks (SNNs). However, such accelerators are vulnerable to transient faults (i.e., soft errors), which occur due…

Hardware Architecture · Computer Science 2023-03-06 Rachmad Vidya Wicaksana Putra , Muhammad Abdullah Hanif , Muhammad Shafique

Single-event upset (SEU) fault tolerance for systems-on-chip (SoCs) in radiation-heavy environments is often addressed by architectural fault-tolerance approaches protecting individual SoC components (e.g., cores, memories) in isolation.…

Hardware Architecture · Computer Science 2026-03-30 Michael Rogenmoser , Philippe Sauter , Chen Wu , Angelo Garofalo , Luca Benini

Whereas contemporary Error Correcting Codes (ECC) designs occupy a significant fraction of total die area in chip-multiprocessors (CMPs), approaches to deal with the vulnerability increase of CMP architecture against Single Event Upsets…

Hardware Architecture · Computer Science 2016-07-29 Navid Khoshavi , Armin Samiei

PUBLISHED ON IEEE/ASME TRANSACTIONS ON MECHATRONICS, DOI: 10.1109/TMECH.2021.3100150. Ideally, accurate sensor measurements are needed to achieve a good performance in the closed-loop control of mechatronic systems. As a consequence, sensor…

Systems and Control · Electrical Eng. & Systems 2021-12-02 Daulet Baimukashev , Bexultan Rakhim , Matteo Rubagotti , Huseyin Atakan Varol

Fault tolerance is a critical aspect of modern computing systems, ensuring correct functionality in the presence of faults. This paper presents a comprehensive survey of fault tolerance methods and software-based mitigation techniques in…

Systems and Control · Electrical Eng. & Systems 2024-04-17 Mohammadreza Amel Solouki , Shaahin Angizi , Massimo Violante

Radiation-induced soft errors are one of the most challenging issues in Safety Critical Real-Time Embedded System (SACRES) reliability, usually handled using different flavors of Double Modular Redundancy (DMR) techniques. This solution is…

Hardware Architecture · Computer Science 2023-08-31 Deniz Kasap , Alessio Carpegna , Alessandro Savino , Stefano Di Carlo

Thermal management in 3D ICs is increasingly challenging due to higher power densities. Traditional PDE-solving-based methods, while accurate, are too slow for iterative design. Machine learning approaches like FNO provide faster…

Machine Learning · Computer Science 2025-10-21 Zhen Huang , Hong Wang , Wenkai Yang , Muxi Tang , Depeng Xie , Ting-Jung Lin , Yu Zhang , Wei W. Xing , Lei He

Rising complexity of in-vehicle electronics is enabling new capabilities like autonomous driving and active safety. However, rising automation also increases risk of security threats which is compounded by lack of in-built security measures…

Cryptography and Security · Computer Science 2024-01-22 Shashwat Khandelwal , Eashan Wadhwa , Shreejith Shanker

With increasing aging problems of advanced technologies, in-field testing becomes an inevitable challenge, on top of the already demanding requirements, such as the ISO26262 for automotive safety. SOCs used in space, automotive or military…

Hardware Architecture · Computer Science 2024-12-31 Tobias Strauch

A large share of today's HPC workloads is used for Ab-Initio Molecular Dynamics (AIMD) simulations, where the interatomic forces are computed on-the-fly by means of accurate electronic structure calculations. They are computationally…

Distributed, Parallel, and Cluster Computing · Computer Science 2020-06-16 Arjun Ramaswami , Tobias Kenter , Thomas D. Kühne , Christian Plessl

Discrete Event Simulation is a widely used technique that is used to model and analyze complex systems in many fields of science and engineering. The increasingly large size of simulation models poses a serious computational challenge,…

Distributed, Parallel, and Cluster Computing · Computer Science 2016-12-30 Gabriele D'Angelo , Stefano Ferretti , Moreno Marzolla , Lorenzo Armaroli

The risk of soft errors due to radiation continues to be a significant challenge for engineers trying to build systems that can handle harsh environments. Building systems that are Radiation Hardened by Design (RHBD) is the preferred…

Hardware Architecture · Computer Science 2020-01-23 Sai Aparna Aketi , Smriti Gupta , Huimei Cheng , Joycee Mekie , Peter A. Beerel

Alpha-particles and cosmic rays cause bit flips in chips. Protection circuits ease the problem, but cost chip area and power, and so designers try hard to optimize them. This leads to bugs: an undetected fault can bring miscalculations, the…

Other Computer Science · Computer Science 2017-12-13 Patrick Klampfl , Robert Koenighofer , Roderick Bloem , Ayrat Khalimov , Aiman Abu-Yonis , Shiri Moran

The Functional Failure Rate analysis of today's complex circuits is a difficult task and requires a significant investment in terms of human efforts, processing resources and tool licenses. Thereby, de-rating or vulnerability factors are a…

Signal Processing · Electrical Eng. & Systems 2020-02-27 Thomas Lange , Aneesh Balakrishnan , Maximilien Glorieux , Dan Alexandrescu , Luca Sterpone

Experimental particle physics demands a sophisticated trigger and acquisition system capable to efficiently retain the collisions of interest for further investigation. Heterogeneous computing with the employment of FPGA cards may emerge as…

High Energy Physics - Experiment · Physics 2023-12-20 Andrea Coccaro , Francesco Armando Di Bello , Stefano Giagu , Lucrezia Rambelli , Nicola Stocchetti

Deep Neural Network (DNN) accelerators are extensively used to improve the computational efficiency of DNNs, but are prone to faults through Single-Event Upsets (SEUs). In this work, we present an in-depth analysis of the impact of SEUs on…

Hardware Architecture · Computer Science 2024-05-27 Naïn Jonckers , Toon Vinck , Gert Dekkers , Peter Karsmakers , Jeffrey Prinzie