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The use of Dynamic Random Access Memory (DRAM) for storing Machine Learning (ML) models plays a critical role in accelerating ML inference tasks in the next generation of communication systems. However, periodic refreshment of DRAM results…

Networking and Internet Architecture · Computer Science 2025-10-31 Junya Shiraishi , Shashi Raj Pandey , Israel Leyva-Mayorga , Petar Popovski

The current flash memory technology focuses on the cost minimization of its static storage capacity. However, the resulting approach supports a relatively small number of program-erase cycles. This technology is effective for consumer…

Information Theory · Computer Science 2015-01-05 Eyal En Gad , Eitan Yaakobi , Anxiao , Jiang , Jehoshua Bruck

This correspondence paper investigates joint design of small base station (SBS) clustering, multicast beamforming for access and backhaul links, as well as frequency allocation in backhaul transmission to minimize the total power…

Signal Processing · Electrical Eng. & Systems 2019-09-04 Jun Xu , Pengcheng Zhu , Jiamin Li , Xiaohu You

Memory bandwidth is known to be a performance bottleneck for FPGA accelerators, especially when they deal with large multi-dimensional data-sets. A large body of work focuses on reducing of off-chip transfers, but few authors try to improve…

Hardware Architecture · Computer Science 2024-01-23 Corentin Ferry , Nicolas Derumigny , Steven Derrien , Sanjay Rajopadhye

Prices of NAND flash memories are falling drastically due to market growth and fabrication process mastering while research efforts from a technological point of view in terms of endurance and density are very active. NAND flash memories…

Hardware Architecture · Computer Science 2012-09-17 Jalil Boukhobza , Pierre Olivier , Stéphane Rubini

The number of battery-powered devices is rapidly increasing due to the widespread use of IoT-enabled nodes in various fields. Energy harvesters, which help to power embedded devices, are a feasible alternative to replacing battery-powered…

Hardware Architecture · Computer Science 2023-05-18 SatyaJaswanth Badri , Mukesh Saini , Neeraj Goel

The emergence of Phase-Change Memory (PCM) provides opportunities for directly connecting persistent memory to main memory bus. While PCM achieves high read throughput and low standby power, the critical concerns are its poor write…

Hardware Architecture · Computer Science 2020-07-28 Yinjin Fu

In this paper, we investigate energy-efficient clustering and medium access control (MAC) for cellular-based M2M networks to minimize device energy consumption and prolong network battery lifetime. First, we present an accurate energy…

Information Theory · Computer Science 2016-08-25 Guowang Miao , Amin Azari , Taewon Hwang

Processing-in-memory (PIM) architectures bring computation closer to data, reducing the processor-memory transfer bottleneck in traditional processor-centric designs. Novel hardware solutions, such as UPMEM's in-memory processing…

Emerging Technologies · Computer Science 2026-04-10 Peterson Yuhala , Mpoki Mwaisela , Pascal Felber , Valerio Schiavoni

In this paper, to address backhaul capacity bottleneck and concurrently optimize energy consumption and delay, we formulate a novel weighted-sum multi-objective optimization problem where popular content caching placement and integrated…

Optimization and Control · Mathematics 2022-01-21 Wen Shang , Vasilis Friderikos

We formulate and solve the energy minimization problem for a clustered device-to-device (D2D) network with cache-enabled mobile devices. Devices are distributed according to a Poisson cluster process (PCP) and are assumed to have a surplus…

Distributed, Parallel, and Cluster Computing · Computer Science 2018-08-10 Ramy Amer , M. Majid Butt , Hesham ElSawy , Mehdi Bennis , Jacek Kibiłda , Nicola Marchetti

Relaxed retention (or volatile) spin-transfer torque RAM (STT-RAM) has been widely studied as a way to reduce STT-RAM's write energy and latency overheads. Given a relaxed retention time STT-RAM level one (L1) cache, we analyze the impacts…

Computers and Society · Computer Science 2024-07-30 Dhruv Gajaria , Tosiron Adegbija

The rapid growth of deep neural network (DNN) workloads has significantly increased the demand for large-capacity on-chip SRAM in machine learning (ML) applications, with SRAM arrays now occupying a substantial fraction of the total die…

Hardware Architecture · Computer Science 2025-12-30 Subhradip Chakraborty , Ankur Singh , Xuming Chen , Gourav Datta , Akhilesh R. Jaiswal

Battery-less technology evolved to replace battery technology. Non-volatile memory (NVM) based processors were explored to store the program state during a power failure. The energy stored in a capacitor is used for a backup during a power…

Hardware Architecture · Computer Science 2023-05-02 SatyaJaswanth Badri , Mukesh Saini , Neeraj Goel

With the imminent slowing down of DRAM scaling, Phase Change Memory (PCM) is emerging as a lead alternative for main memory technology. While PCM achieves low energy due to various technology-specific advantages, PCM is significantly slower…

Hardware Architecture · Computer Science 2015-04-17 Hamza Bin Sohail , Balajee Vamanan , T. N. Vijaykumar

On-device learning has emerged as a promising direction for AI development, particularly because of its potential to reduce latency issues and mitigate privacy risks associated with device-server communication, while improving energy…

Machine Learning · Computer Science 2025-07-25 Le-Trung Nguyen , Ael Quelennec , Van-Tam Nguyen , Enzo Tartaglione

This letter investigates a cache-enabled multiuser mobile edge computing (MEC) system with dynamic task arrivals, taking into account the impact of proactive cache placement on the system's overall energy consumption. We consider that an…

Information Theory · Computer Science 2023-02-01 Jingxuan Liang , Hong Xing , Feng Wang , Vincent K. N. Lau

To index the increasing volume of data, modern data indexes are typically stored on SSDs and cached in DRAM. However, searching such an index has resulted in significant I/O traffic due to limited access locality and inefficient cache…

Hardware Architecture · Computer Science 2024-08-05 Yun-Chih Chen , Yuan-Hao Chang , Tei-Wei Kuo

Network management protocols often require timely and meaningful insight about per flow network traffic. This paper introduces Randomized Admission Policy (RAP) - a novel algorithm for the frequency and top-k estimation problems, which are…

Data Structures and Algorithms · Computer Science 2016-12-12 Ran Ben Basat , Gil Einziger , Roy Friedman , Yaron Kassner

Unbalanced optimal transport (UOT) has been widely used as a fundamental tool in many application domains, where it often dominates the application running time. While many researchers have proposed various optimizations for UOT, few have…

Distributed, Parallel, and Cluster Computing · Computer Science 2024-12-17 Chengyu Sun , Jinyu Hu , Hong Jiang