Related papers: On-Chip Test Infrastructure Design for Optimal Mul…
As the landscape of devices that interact with the electrical grid expands, also the complexity of the scenarios that arise from these interactions increases. Validation methods and tools are typically domain specific and are designed to…
For nanotechnology nodes, the feature size is shrunk rapidly, the wire becomes narrow and thin, it leads to high RC parasitic, especially for resistance. The overall system performance are dominated by interconnect rather than device. As…
Advancements in multi-core have created interest among many research groups in finding out ways to harness the true power of processor cores. Recent research suggests that on-board component such as cache memory plays a crucial role in…
Modern powerful reconfigurable systems are suited in the implementation of various data-stream, data-parallel, and other applications. An application that needs real-time, fast, and reliable data processing is the global positioning system…
Today, there are a plethora of In-Memory Computing (IMC) devices- SRAMs, PCMs & FeFETs, that emulate convolutions on crossbar-arrays with high throughput. Each IMC device offers its own pros & cons during inference of Deep Neural Networks…
A major security challenge for modern Internet of Things (IoT) deployments is to ensure that the devices run legitimate firmware free from malware. This challenge can be addressed through a security primitive called attestation which allows…
Internet of Things (IoT) systems continuously collect a large amount of data from heterogeneous "smart objects" through standardised service interfaces. A key challenge is how to use these data and relevant event logs to construct…
A high accuracy and high sensitivity system architecture is proposed for the read-out circuit of electrical impedance tomography system-on-chip. The switched ratiometric technique is applied in the proposed architecture. The proposed system…
Training large language models (LLMs) imposes extreme demands on computation, memory capacity, and interconnect bandwidth, driven by their ever-increasing parameter scales and intensive data movement. Wafer-scale integration offers a…
Coflow provides a key application-layer abstraction for capturing communication patterns, enabling the efficient coordination of parallel data flows to reduce job completion times in distributed systems. Modern data center networks (DCNs)…
We report the fabrication and study of Hall bar MOSFET devices in which an overlapping-gate architecture allows four-terminal measurements of low-density 2D electron systems, while maintaining a high density at the ohmic contacts.…
On-chip communication infrastructure is a central component of modern systems-on-chip (SoCs), and it continues to gain importance as the number of cores, the heterogeneity of components, and the on-chip and off-chip bandwidth continue to…
Regression testing assures software correctness after changes but is resource-intensive. Test Case Prioritisation (TCP) mitigates this by ordering tests to maximise early fault detection. Diversity-based TCP prioritises dissimilar tests,…
The Scaling of microchip technologies, from micron to submicron and now to deep sub-micron (DSM) range, has enabled large scale systems-on-chip (SoC). In future deep submicron (DSM) designs, the interconnect effect will definitely dominate…
Effective mixing is essential for biochemical reactions. In droplet-based microfluidics, immediate mixing of substances upon contact in the droplet formation stage can greatly enhance the uniformity of chemical reactions. Furthermore, it…
Most atomic physics experiments are controlled by a digital pattern generator used to synchronize all equipment by providing triggers and clocks. Recently, the availability of well-documented open-source development tools has lifted the…
In this paper, we examine the different measures of Fault Tolerance in a Distributed Simulated Annealing process. Optimization by Simulated Annealing on a distributed system is prone to various sources of failure. We analyse simulated…
Tunneling field-effect transistors (TFETs) based on 2D materials are promising steep sub-threshold swing (SS) devices due to their tight gate control. There are two major methods to create the tunnel junction in these 2D TFETs: electrical…
In this paper, we demonstrate by simulation the general usability of an electrostatically doped and electrically reconfigurable planar field-effect transistor (FET) structure. The device concept is partly based on our already published and…
Rapid CMOS device size reduction resulted in billions of transistors on a chip have led to integration of many cores leading to many challenges such as increased power dissipation, thermal dissipation, occurrence of transient faults and…