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When Monte-Carlo Dropout Meets Multi-Exit: Optimizing Bayesian Neural Networks on FPGA

Machine Learning 2023-08-15 v1 Hardware Architecture

Abstract

Bayesian Neural Networks (BayesNNs) have demonstrated their capability of providing calibrated prediction for safety-critical applications such as medical imaging and autonomous driving. However, the high algorithmic complexity and the poor hardware performance of BayesNNs hinder their deployment in real-life applications. To bridge this gap, this paper proposes a novel multi-exit Monte-Carlo Dropout (MCD)-based BayesNN that achieves well-calibrated predictions with low algorithmic complexity. To further reduce the barrier to adopting BayesNNs, we propose a transformation framework that can generate FPGA-based accelerators for multi-exit MCD-based BayesNNs. Several novel optimization techniques are introduced to improve hardware performance. Our experiments demonstrate that our auto-generated accelerator achieves higher energy efficiency than CPU, GPU, and other state-of-the-art hardware implementations.

Keywords

Cite

@article{arxiv.2308.06849,
  title  = {When Monte-Carlo Dropout Meets Multi-Exit: Optimizing Bayesian Neural Networks on FPGA},
  author = {Hongxiang Fan and Hao Chen and Liam Castelli and Zhiqiang Que and He Li and Kenneth Long and Wayne Luk},
  journal= {arXiv preprint arXiv:2308.06849},
  year   = {2023}
}
R2 v1 2026-06-28T11:54:43.390Z