Voltage Mode Winner-Take-All Circuit for Neuromorphic Systems
Artificial Intelligence
2025-07-08 v1
Abstract
Recent advances in neuromorphic computing demonstrate on-device learning capabilities with low power consumption. One of the key learning units in these systems is the winner-take-all circuit. In this research, we propose a winner-take-all circuit that can be configured to achieve k-winner and hysteresis properties, simulated in IBM 65 nm node. The circuit dissipated 34.9 W of power with a latency of 10.4 ns, while processing 1000 inputs. The utility of the circuit is demonstrated for spatial filtering and classification.
Keywords
Cite
@article{arxiv.2507.04338,
title = {Voltage Mode Winner-Take-All Circuit for Neuromorphic Systems},
author = {Abdullah M. Zyarah and Dhireesha Kudithipudi},
journal= {arXiv preprint arXiv:2507.04338},
year = {2025}
}