Failure triage in design functional verification is critical but time-intensive, relying on manual specification reviews, log inspections, and waveform analyses. While machine learning (ML) has improved areas like stimulus generation and coverage closure, its application to RTL-level simulation failure triage, particularly for large designs, remains limited. VCDiag offers an efficient, adaptable approach using VCD data to classify failing waveforms and pinpoint likely failure locations. In the largest experiment, VCDiag achieves over 94% accuracy in identifying the top three most likely modules. The framework introduces a novel signal selection and statistical compression approach, achieving over 120x reduction in raw data size while preserving features essential for classification. It can also be integrated into diverse Verilog/SystemVerilog designs and testbenches.
@article{arxiv.2506.03590,
title = {VCDiag: Classifying Erroneous Waveforms for Failure Triage Acceleration},
author = {Minh Luu and Surya Jasper and Khoi Le and Evan Pan and Michael Quinn and Aakash Tyagi and Jiang Hu},
journal= {arXiv preprint arXiv:2506.03590},
year = {2025}
}