English

Understanding LLM Checkpoint/Restore I/O Strategies and Patterns

Distributed, Parallel, and Cluster Computing 2026-01-01 v1

Abstract

As LLMs and foundation models scale, checkpoint/restore has become a critical pattern for training and inference. With 3D parallelism (tensor, pipeline, data), checkpointing involves many processes, each managing numerous tensors of varying shapes and sizes, that must be persisted frequently to stable storage (e.g., parallel file systems). This turns checkpoint/restore into a big-data I/O problem characterized by volume, variety, and velocity. The workflow must traverse the full storage stack -- from GPU memory through host memory and local storage to external repositories -- whose tiers differ by orders of magnitude in performance, creating bottlenecks under concurrency even with asynchronous flush/prefetch. Kernel-accelerated I/O libraries such as \texttt{liburing} may mitigate these issues versus POSIX, but their effectiveness for LLM checkpointing remains underexplored. We develop microbenchmarks to quantify trade-offs when using \texttt{liburing}, evaluating how aggregation, alignment, and I/O coalescing interact under buffered and direct I/O. We find that uncoalesced small-buffer operations halve throughput relative to synthetic workloads, while file system-aware aggregation restores bandwidth and reduces metadata overhead. Compared to state-of-the-art LLM checkpointing engines, our approach achieves up to 3.9×3.9\times higher write throughput than DataStates-LLM and 7.6×7.6\times higher than TorchSnapshot. These results highlight the need for aggregation and coalescing strategies that align with modern file systems and I/O backends.

Keywords

Cite

@article{arxiv.2512.24511,
  title  = {Understanding LLM Checkpoint/Restore I/O Strategies and Patterns},
  author = {Mikaila J. Gossman and Avinash Maurya and Bogdan Nicolae and Jon C. Calhoun},
  journal= {arXiv preprint arXiv:2512.24511},
  year   = {2026}
}

Comments

SCA/HPCAsia 2026 Workshops: Supercomputing Asia and International Conference on High Performance Computing in the Asia Pacific Region Workshops

R2 v1 2026-07-01T08:46:20.603Z