This article starts from the assumption that near future 100BTransistor SuperComputers-on-a-Chip will include N big multi-core processors, 1000N small many-core processors, a TPU-like fixed-structure systolic array accelerator for the most frequently used Machine Learning algorithms needed in bandwidth-bound applications and a flexible-structure reprogrammable accelerator for less frequently used Machine Learning algorithms needed in latency-critical applications.
@article{arxiv.2009.10593,
title = {The Ultimate DataFlow for Ultimate SuperComputers-on-a-Chip, for Scientific Computing, Geo Physics, Complex Mathematics, and Information Processing},
author = {Veljko Milutinovic and Erfan Sadeqi Azer and Kristy Yoshimoto and Gerhard Klimeck and Miljan Djordjevic and Milos Kotlar and Miroslav Bojovic and Bozidar Miladinovic and Nenad Korolija and Stevan Stankovic and Nenad Filipović and Zoran Babovic and Miroslav Kosanic and Akira Tsuda and Mateo Valero and Massimo De Santo and Erich Neuhold and Jelena Skoručak and Laura Dipietro and Ivan Ratkovic},
journal= {arXiv preprint arXiv:2009.10593},
year = {2021}
}