The Architecture of the ZEUS Micro Vertex Detector DAQ and Second Level Global Track Trigger
Abstract
The architecture of the ZEUS Micro Vertex Detector data acquisition system and the implementation of its second level trigger, the ZEUS Global Track Trigger are described. Data from the vertex detectors HELIX read-out chips, corresponding to 200k channels, are digitized by 3 crates of ADCs which perform noise and pedestal subtraction, and data suppression and compaction. PowerPC VME board computers push cluster data for second level trigger processing and strip data for event building via Fast and Gigabit Ethernet network connections. Additional tracking information from the central tracking chamber and the forward straw tube tracker are interfaced into the 12 dual CPU PC farm of the Global Track Trigger where track and vertex finding is performed. The system is data driven at the ZEUS first level trigger rate (~500Hz) and must generate a trigger result after a mean time of 10ms.
Cite
@article{arxiv.physics/0307006,
title = {The Architecture of the ZEUS Micro Vertex Detector DAQ and Second Level Global Track Trigger},
author = {Alessandro Polini},
journal= {arXiv preprint arXiv:physics/0307006},
year = {2011}
}
Comments
Talk from the 2003 Computing in High Energy and Nuclear Physics (CHEP03), La Jolla, Ca, USA, March 2003, 10 pagfes, LaTex, 11 eps figures. PSN MOGT005