Tejas Simulator : Validation against Hardware

Smruti R. Sarangi; Rajshekar Kalayappan; Prathmesh Kallurkar; Seep Goel

Tejas Simulator : Validation against Hardware

Hardware Architecture 2015-01-30 v1

Authors: Smruti R. Sarangi , Rajshekar Kalayappan , Prathmesh Kallurkar , Seep Goel

Abstract

In this report we show results that validate the Tejas architectural simulator against native hardware. We report mean error rates of 11.45% and 18.77% for the SPEC2006 and Splash2 benchmark suites respectively. These error rates are competitive and in most cases better than the numbers reported by other contemporary simulators.

Tejas Simulator : Validation against Hardware

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