Synchronization Processor Synthesis for Latency Insensitive Systems
Hardware Architecture
2011-11-09 v1
Abstract
In this paper we present our contribution in terms of synchronization processor for a SoC design methodology based on the theory of the latency insensitive systems (LIS) of Carloni et al. Our contribution consists in IP encapsulation into a new wrapper model which speed and area are optimized and synthetizability guarantied. The main benefit of our approach is to preserve the local IP performances when encapsulating them and reduce SoC silicon area.
Keywords
Cite
@article{arxiv.0710.4659,
title = {Synchronization Processor Synthesis for Latency Insensitive Systems},
author = {Pierre Bomel and Eric Martin and Emmanuel Boutillon},
journal= {arXiv preprint arXiv:0710.4659},
year = {2011}
}
Comments
Submitted on behalf of EDAA (http://www.edaa.com/)