English

Support Vector Machines Classification on Bendable RISC-V

Hardware Architecture 2025-08-28 v1

Abstract

Flexible Electronics (FE) technology offers uniquecharacteristics in electronic manufacturing, providing ultra-low-cost, lightweight, and environmentally-friendly alternatives totraditional rigid electronics. These characteristics enable a rangeof applications that were previously constrained by the costand rigidity of conventional silicon technology. Machine learning (ML) is essential for enabling autonomous, real-time intelligenceon devices with smart sensing capabilities in everyday objects. However, the large feature sizes and high power consumption ofthe devices oppose a challenge in the realization of flexible ML applications. To address the above, we propose an open-source framework for developing ML co-processors for the Bendable RISC-V core. In addition, we present a custom ML accelerator architecture for Support Vector Machine (SVM), supporting both one-vs-one (OvO) and one-vs-rest (OvR) algorithms. Our ML accelerator adopts a generic, precision-scalable design, supporting 4-, 8-, and 16-bit weight representations. Experimental results demonstrate a 21x improvement in both inference execution time and energy efficiency, on average, highlighting its potential for low-power, flexible intelligence on the edge.

Keywords

Cite

@article{arxiv.2508.19656,
  title  = {Support Vector Machines Classification on Bendable RISC-V},
  author = {Polykarpos Vergos and Theofanis Vergos and Florentia Afentaki and Konstantinos Balaskas and Georgios Zervakis},
  journal= {arXiv preprint arXiv:2508.19656},
  year   = {2025}
}

Comments

Accepted for publication at the IEEE Computer Society Annual Symposium on VLSI (ISVLSI '25)

R2 v1 2026-07-01T05:08:01.224Z