The hardware transactional memory (HTM) implementations in commercially available processors are significantly hindered by their tight capacity constraints. In practice, this renders current HTMs unsuitable to many real-world workloads of in-memory databases. This paper proposes SI-HTM, which stretches the capacity bounds of the underlying HTM, thus opening HTM to a much broader class of applications. SI-HTM leverages the HTM implementation of the IBM POWER architecture with a software layer to offer a single-version implementation of Snapshot Isolation. When compared to HTM- and software-based concurrency control alternatives, SI-HTM exhibits improved scalability, achieving speedups of up to 300% relatively to HTM on in-memory database benchmarks.
@article{arxiv.2003.03317,
title = {Stretching the capacity of Hardware Transactional Memory in IBM POWER architectures},
author = {Ricardo Filipe and Shady Issa and Paolo Romano and João Barreto},
journal= {arXiv preprint arXiv:2003.03317},
year = {2020}
}